Basic cell, standard cell, standard cell library, back-end full-custom design method and chip

Abstract

The invention discloses a basic cell, standard cell, standard cell library and back-end full-custom design method and a chip manufactured based on the method, and belongs to the technical field of integrated circuit layout designs. The basic cell disclosed by the invention at least comprises GATE layers, ACT layers, an LVNW layer, NPULS layers and PPLUS layers as well as a CT layer and a METAL layer which are all in regular shapes; the regular shapes of the GATE layers, the ACT layers, the LVNW layer, the NPULS layers and the PPLUS layers all need to meet process design rules. The layout of the standard cell comprises M basic cells in different Metal wiring manners, and M is a nonzero integer. The standard cell library comprises a plurality of the standard cells with different functions. The back-end full-custom design method of the invention comprises the following steps: determining the standard cell library, designing the chip based on the standard cell, carrying out analog simulation on a module layout and outputting the layout. The chip realized by adopting the back-end full-custom layout design method is more regular and standard in design to greatly optimize the layout design and improve the layout and processing efficiency so as to shorten the product time to market.

Description

technical field [0001] The invention relates to the technical field of integrated circuit layout design, in particular to a basic unit, a standard unit, a standard unit library, a back-end fully customized design method and a chip realized by the method. Background technique [0002] Integrated circuit layout design includes design based on standard cell library. The design of the standard cell library refers to the design of some standard cells (such as combinational logic, sequential logic, physical cells, etc.) When designing the circuit, call the required standard cells from the standard cell library according to the circuit requirements, and carry out logic synthesis and automatic layout and routing. [0003] The layout design of the standard cell library in the prior art only determines the basic parameters of the layout design according to the relevant process parameters and the technical indicators of the cell library, such as the cell height, line width, wiring cha...

AI Technical Summary

Problems solved by technology

If it is processed according to the layout design of the standard cell library in the prior art, it takes 2 days for each layer of the mask, and if there are 26 layers in total, it takes 52 days for the successful manufacture

First of all, its irregular layout increases the difficulty of processing a single chip and prolongs the processing time of a single chip, not to mention the mass production of chips, which cannot meet the demand for market investment in a timely manner; Processing with the layout design of the standard cell library in technology is equivalent to going through the entire processing process again. The processing efficiency is low, and new products cannot be launched in time, and the market competition of enterprises loses the opportunity

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