Two-stage time-to-digital converter

Abstract

The invention belongs to the field of microelectronics and time measurement, and particularly relates to a two-stage time-to-digital converter. The circuits of the converter can be applied to all digital phase-locked loops (ADPLL) with high frequency wide bands. According to the two-stage time-to-digital converter of the invention, the combination of semi custom and full custom is adopted, and two-stage time-to-digital converter comprises a first-stage quantizing structure, a time deviation selection circuit, a second-stage quantizing structure and a decoding circuit, wherein the first-stage quantizing structure adopts a buffer delay chain for coarse quantization; the time deviation selection circuit is composed of a selective signal generator, a delay chain and a multiplexer; the second-stage quantizing structure adopts a Vernier delay chain using a buffer as a basic unit to carry out fine quantization, and a duplication chain comprising a first-stage buffer chain simultaneously multiplexes the Vernier delay chain for measurement of a resolution ratio; the decoding circuit corresponds to a quantization scheme to realize transformation from pseudo thermometer codes to binary codes; the selective signal generator and the decoding circuit are realized by Verilog semi-custom, and the rest are realized by full-custom. The two-stage time-to-digital converter of the invention can be applied to ADPLL with the high frequency wide bands so as to realize time-to-digital conversion with high resolution and linearity.

Description

technical field [0001] The invention belongs to the field of microelectronics and time measurement, and in particular relates to a two-stage time-to-digital converter. The circuit of the converter can be applied to a high-frequency and wide-band all-digital phase-locked loop. Background technique [0002] With the advancement of process reduction, a time-to-digital converter (Time to Digital Converter, TDC) can achieve higher and higher resolutions. The prior art discloses that the time-to-digital converter TDC is the key to the digitization of a phase-locked loop (PLL, Phase Lock Loop). Generally, digital PLL (DPLL, Digital PLL) includes counter-assisted all-digital phase-locked loop (ADPLL, All Digital PLL) and frequency divider-assisted DPLL, the latter is hindered by high-frequency limitations and the complexity of frequency divider design Full digital implementation. [0003] According to research reports, the TDC used in the counter-assisted ADPLL is to measure the i...

AI Technical Summary

Problems solved by technology

[0005] At present, the difficulty of the two-stage TDC applied to the high-frequency broadband ADPLL is that the high-frequency broadband signal is used as an input terminal, which leads to the complexity of time quantization, and the measurement of the high-frequency signal period

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