99 results about "Time to digital conversion" patented technology

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

A detector (22) detects an event. First and second time-to-digital converters(TDCs) (70, 72) generate first and second time stamps (TS1, TS2) for the detection of the event. The first TDC and the second TDC are both synchronized with a common clock signal (62) that defines a fixed time offset between the second TDC and the first TDC. An autocalibration circuit (120) adjusts the first TDC and the second TDC to keep the time difference between the second time stamp and the first time stamp equal to the fixed time offset between the second TDC and the first TDC. The detector may be a detector array, and trigger circuitry (28) propagates a trigger signal from a triggering detector of the array of detectors to the first and second TDC's. Skew correction circuitry (132, 134, 136, 142, 60, 162) adjusts a timestamp (TS) based on which detector is the triggering detector.

The present invention relates to a time digital converter, and more particularly, to a noise-shaping time to digital converter (TDC) that has a 1-bit output and uses a delta-sigma modulation method. The noise-shaping time to digital converter (TDC) that has the 1-bit output and uses the delta-sigma modulation method in accordance with the present invention eliminates the need for a large number of D flip-flops or counters and a plurality of delay units connected in series to one another because the time to digital converter is fabricated such that a delay element has a resolution of the effective delay time in a semiconductor process, unlike the conventional time to digital converter. Therefore, the time to digital converter of the present invention has an advantage in that an extremely high resolution and high linearity can be achieved with an efficient circuit configuration and low power consumption.

This invention relates to a measuring method and device of impulse form. The invention includes one constant proportion timing discriminate module and one time-to-digital conversion module. Data of time-to-digital conversion modular enter calculator for handling. Constant proportion timing discriminate module has a group of leading edge discriminator and a group of back edge discriminator, which separately discriminate a series of points where the ratio of pulse front edge and back edge voltage and spike voltage are certain worth corresponding time. multipass time-to-digital conversion module convert time interval between first time and subsequently time to digital quantity, adopt digital counting method and combine digital delay line bracketing method, realize at a piece of field programmable logic array FPGA. sending obtained data into computer for calculation to gain time interval, base on voltage peak ratio of every time to indirectly reduce impulse form, and obtain pulsewidth. The invention has low cost, small bulk, and light weight, can apply to laser range finder.

A time to digital converter includes: a delay circuit having a plurality of delay stages that delay an input clock signal in multiple stages, at least one of the delay stages being a variable delay stage; a plurality of flip flops that capture outputs of the delay stages corresponding thereto in a one-to-one relation in response to input of a reference signal; an edge detecting circuit that detects changing edges of respective outputs of the flip flops; a counter circuit that counts a number of edges detected by the edge detecting circuit; and a control circuit that controls a delay amount of the variable delay stage according to the number of edges counted by the counter circuit.

The invention belongs to the field of microelectronics and time measurement, and particularly relates to a two-stage time-to-digital converter. The circuits of the converter can be applied to all digital phase-locked loops (ADPLL) with high frequency wide bands. According to the two-stage time-to-digital converter of the invention, the combination of semi custom and full custom is adopted, and two-stage time-to-digital converter comprises a first-stage quantizing structure, a time deviation selection circuit, a second-stage quantizing structure and a decoding circuit, wherein the first-stage quantizing structure adopts a buffer delay chain for coarse quantization; the time deviation selection circuit is composed of a selective signal generator, a delay chain and a multiplexer; the second-stage quantizing structure adopts a Vernier delay chain using a buffer as a basic unit to carry out fine quantization, and a duplication chain comprising a first-stage buffer chain simultaneously multiplexes the Vernier delay chain for measurement of a resolution ratio; the decoding circuit corresponds to a quantization scheme to realize transformation from pseudo thermometer codes to binary codes; the selective signal generator and the decoding circuit are realized by Verilog semi-custom, and the rest are realized by full-custom. The two-stage time-to-digital converter of the invention can be applied to ADPLL with the high frequency wide bands so as to realize time-to-digital conversion with high resolution and linearity.

The invention discloses an unbiased random number generator. The unbiased random number generator comprises an APD (Avalanche Photo Diode) module, an avalanche signal discriminating, shaping and amplifying module, a time-to-digital conversion module and an encoder module, wherein electronic pulse generated by the APD module is encoded to generate a random sequence. The invention discloses an unbiased random number generation method and an unbiased random number generator chip. The generated random number sequence can pass random statistical detection without complex post-processing processes. The device and the method have extremely high integration level, and the device can be packaged into a chip-level device by using an integrated circuit process. The device and the method can work without light source, and light quantum generated by an external light source can also be coupled though an optical fiber or free space to adjust the generation efficiency of the random number. Thus, the device and the method have good compatibility with the environment and can normally work without special working conditions such as low temperature and tight shading.

A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal.

The invention provides a successive approximation ADC comparator based on time domain, which belongs to the technical field of data converters. The comparator is characterized in that the comparator consists of a voltage time conversion circuit of voltage control delay, a positive feedback time-to-digital conversion circuit and a level RS latch in sequential series connection; as the comparator adopts a time-to-digital conversion technique and replaces a DFF trigger with the level RS latch, the comparator can distinguish input voltage difference lower than 10 mu V at a speed of 60 MHz; in addition, the comparator uses no resistor or capacitor elements, thereby having small area and low power consumption.

The invention discloses a time to digital converter which comprises a time to digital converting unit, a digital to time converting unit and a time amplifier. The time to digital converting unit is used for digitally quantizing time so as to achieve a time digital quantization function. The digital to time converting unit is used for extracting the time margin part which is smaller than the quantization time unit and not be quantized. The time amplifier is used for linearly amplifying the time margin part extracted by the digital to time converting unit so as to further conduct digital quantization. By means of the time to digital converter, the performance requirements of high time precision, wide measuring range, high converting rate and the like can be met. The time to digital converter can improve the precision and speed of time to digital conversion when applied in the technical application field of time mode signal processing.

The invention provides a time-to-digital conversion circuit, which comprises a first delay circuit, a second delay circuit, a first counter, a second counter and a comparator, wherein the first delay circuit is provided with a first delay level and used for delaying a first input signal to generate a first output signal; the second delay circuit is provided with a second delay level and used for delaying a second input signal to generate a second output signal; the first counter is used for counting the first output signal to generate a first counting value; the second counter is used for counting the second output signal to generate a second counting value; the comparator is used for comparing the first counting value with the second counting value to generate a comparison result signal; the first delay level has larger delay quantity than the second delay level; the first counter begins to count earlier compared with the second counter; and when the second counting value is within a preset range comprising the first counting value, the comparator outputs the comparison result signal.

The invention relates to the analog to digital conversion technology, and aims to reduce the conversion time of a column-level single-slope ADC for a high scanning speed linear CIS without a significant increase in the area and power consumption. To this end, the invention adopts a technical scheme of a column-level ADC for a high-speed linear CMOS image sensor, and the column-level ADC is formed by series connection of an analog voltage to time converter (ATC) and a time to digital converter. The analog voltage to time converter ATC is constructed as follows: an input signal is connected to a same-phase end through a switch S4 and an S/H; and a current source positive end is connected through a capacitor to an OPA amplifier anti-phase end and is further connected through a switch S1 to bias voltage and an OPA amplifier same-phase end, a current source negative end is grounded, an OPA amplifier output end is connected with an anti-phase end, a switch S2 is disposed between the OPA amplifier output end and the anti-phase end, and a C1 is disposed between the OPA amplifier output end and the current source positive end. The invention is mainly applied to analog to digital conversion.

The invention discloses an all-digital phase-locked ring applicable to video signal processing, comprising an analog-to-digital conversion circuit ADC, an automatic gain control circuit AGC, a digital low-pass filter DLPF, a synchronous header split circuit, a frequency detector FD, a time-to-digital conversion circuit TDC, a coarse tuning filter, a phase detector PD, a fine tuning filter, a summator, a digital-controlled oscillator and a pixel frequency divider circuit. The phase detector, the time-to-digital conversion circuit, the coarse tuning filter, the digital-controlled oscillator and the pixel frequency divider circuit constitute a frequency locking loop circuit, and the locking process of the all-digital phase-locked ring is accelerated. The analog-to-digital conversion circuit, the automatic gain control circuit, the digital low-pass filter, the frequency detector, the phase detector, the fine tuning filter, the digital-controlled oscillator and the pixel frequency divider circuit constitute a phase locking loop circuit, and the phase locking loop circuit is used for accurately locking the phase of a synchronous header in an analogue video signal.

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

The invention provides a time-to-digital conversion circuit based on multiple sampling, including enable reset signal generation module, Start delay loop, Stop delay loop, signal detector, Start delayloop and Stop delay loop counter, counter register, ROM memory, ROM memory register, data processor and data processor register. Start, At the input circuit of the stop signal, Propagate into the Start and Stop delay loops, respectively. The last delay cell of each delay loop is followed by a counter. Output connection register, the enable reset signal generation module is connected to the counter. At the same time, the output of each delay loop is connected with 16 signal detectors to sample the signals for many times. The sampling results are input into ROM memory, and the results of outputconnection register, counter register and ROM memory register are used as input and output connection register of data processor. The technical proposal of the invention solves the problem of low measurement accuracy of the existing time-to-digital converter and realizes higher measurement accuracy.

There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.