Successive approximation comparator for ADC based on time domain

Abstract

The invention provides a successive approximation ADC comparator based on time domain, which belongs to the technical field of data converters. The comparator is characterized in that the comparator consists of a voltage time conversion circuit of voltage control delay, a positive feedback time-to-digital conversion circuit and a level RS latch in sequential series connection; as the comparator adopts a time-to-digital conversion technique and replaces a DFF trigger with the level RS latch, the comparator can distinguish input voltage difference lower than 10 mu V at a speed of 60 MHz; in addition, the comparator uses no resistor or capacitor elements, thereby having small area and low power consumption.

Description

technical field [0001] The technical field of direct application of "comparator for successive approximation ADC based on time domain" is ultra-low power consumption analog-to-digital converter circuit design. The proposed circuit is a class of important modules that can be applied to major high-speed low-power ADC structures. Background technique [0002] Wireless sensor networks (WSN) have more and more applications in social and natural environments. Due to the advantages of reliability and accuracy of wireless sensor networks, it is especially focused on the fields of military, national security, medical and environmental observation. Generally, wireless sensor networks are composed of a large number of sensor nodes, which makes power consumption an important constraint in sensor network design, requiring each module in sensor nodes to consume very low energy. [0003] An analog-to-digital converter (ADC) is generally integrated in the WSN node to convert the analog si...

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Problems solved by technology

(See references Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati and Franco Maloberti, "A9.4-ENOB 1V 3.8μW 100kSs SAR ADC with Time_domain comparator", 2008IEEE International Solid-State Circuits Conference). Although the time domain proposed by Andrea Agnes The comparator is simpler and has lower power consumption than the traditional comparator, but it has five major disadvantages: First, the maximum speed of this comparator is only 1.875MHz. This makes the maximum sampling rate of SA R ADC only 100KS / s

The second problem is that because two capacitors and two resistors will increase its area

The third disadvantage is that the power consumption is not low enough

The fourth problem, and possibly the biggest problem, is that the accuracy is relatively poor: only 10 bits or less

The fifth disadvantage is that it can only be used in single-ended circuits

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