Successive approximation comparator for ADC based on time domain

A successive approximation type, comparator technology, applied in instruments, signal transmission systems, electrical components, etc., can solve the problems of low power consumption, increased area, only 1.875MHz, etc., to achieve low dynamic power consumption and working speed. improved effect

Active Publication Date: 2009-08-12
TSINGHUA UNIV
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  • Application Information

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Problems solved by technology

(See references Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati and Franco Maloberti, "A9.4-ENOB 1V 3.8μW 100kSs SAR ADC with Time_domain comparator", 2008IEEE International Solid-State Circuits Conference). Although the time domain proposed by Andrea Agnes The comparator is simpler and has lower power consumption than the traditional comparator, but it has five major disadvantages: First, the maximum speed of this comparator

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  • Successive approximation comparator for ADC based on time domain
  • Successive approximation comparator for ADC based on time domain
  • Successive approximation comparator for ADC based on time domain

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Embodiment Construction

[0023] The technical scheme that the present invention solves its technical problem is: the time domain comparator (TDC) of PFTDT and level latch that the present invention proposes, as image 3 shown. The TDC of the present invention adopts PFTDT for time-to-digital conversion, and then uses a level latch instead of a flip-flop (DFF) to latch the comparison result to improve precision and simultaneously increase the maximum speed of the comparator.

[0024] figure 2Is the traditional time domain comparator circuit. It is mainly composed of two parts: voltage-time converter (VTC) and output D flip-flop. The voltage-time converter consists of two branches: V2T Input and V2TReference. The output of V2T Input is connected to the data terminal (D) of DFF through three inverters (I1, I2 and I3) and the output of V2T Reference is also passed through Three inverters (I4, I5, and I6) are connected to the trigger terminal of the DFF. The operation of the comparator includes two mo...

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Abstract

The invention provides a successive approximation ADC comparator based on time domain, which belongs to the technical field of data converters. The comparator is characterized in that the comparator consists of a voltage time conversion circuit of voltage control delay, a positive feedback time-to-digital conversion circuit and a level RS latch in sequential series connection; as the comparator adopts a time-to-digital conversion technique and replaces a DFF trigger with the level RS latch, the comparator can distinguish input voltage difference lower than 10 mu V at a speed of 60 MHz; in addition, the comparator uses no resistor or capacitor elements, thereby having small area and low power consumption.

Description

technical field [0001] The technical field of direct application of "comparator for successive approximation ADC based on time domain" is ultra-low power consumption analog-to-digital converter circuit design. The proposed circuit is a class of important modules that can be applied to major high-speed low-power ADC structures. Background technique [0002] Wireless sensor networks (WSN) have more and more applications in social and natural environments. Due to the advantages of reliability and accuracy of wireless sensor networks, it is especially focused on the fields of military, national security, medical and environmental observation. Generally, wireless sensor networks are composed of a large number of sensor nodes, which makes power consumption an important constraint in sensor network design, requiring each module in sensor nodes to consume very low energy. [0003] An analog-to-digital converter (ADC) is generally integrated in the WSN node to convert the analog si...

Claims

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Application Information

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IPC IPC(8): H03M1/38
Inventor 克兵格·赛客帝·玻梅杨华中
Owner TSINGHUA UNIV
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