14 results about "Phase time" patented technology

The invention relates to the technical field of integrated circuit low-power-consumption control, and discloses a low-power-consumption control method and system for a fuze chip. The low-power-consumption control method of the fuze chip is applied to chip control equipment, and specifically comprises the following steps: S101, detecting the working state of a functional module electrically connected with the fuze chip within a preset stage time, and judging whether the current state of the functional module is an idle state or not; and S102, if the function module is in the working state, monitoring the operation parameters of the function module, and determining whether the operation parameters of the function module have threshold value changes within the preset stage time. Through precise detection of the idle state of the functional module and delay protection and state verification before the clock is closed, it is ensured that necessary data storage and state synchronization are completed before the functional module enters the low-power-consumption state, system faults caused by sudden interruption of clock signals are avoided, and meanwhile the low-power-consumption requirement and operation reliability are considered.

The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.

The present invention relates to the field of rail transit technology, and in particular to a method and device for determining a train passing through phase position, which is used to solve the problem that there is no method in the prior art specifically for accurately determining the train passing through phase position safely and quickly. The present invention first confirms the position of the neutral section, and obtains the phase section according to the neutral section position; then, according to the phase section analysis, the starting point P1 of the authorized terminal EOA block section inaccessible area and the end point P2 of the authorized terminal EOA block section inaccessible area are obtained, and the starting point P1 and the end point P2 are used as the position of the train passing through phase. The train outputs a phase passing control command when it is a certain time away from the starting point of the phase separation area, and the phase passing control command is canceled after the front of the train passes a certain distance from the end point of the phase separation area, thereby realizing automatic phase passing. The present invention accurately determines the position of the train passing through phase safely and quickly, effectively solves the speed loss problem of the train when passing through the neutral non-powered area of ​​the contact network, significantly shortens the train passing through phase time, and enhances the section passing capacity.

The present invention discloses a DLL phase compensation circuit, which belongs to the field of integrated circuits. The DLL phase compensation circuit adds a clock input port level detection delay simulation unit and a Q port data output drive delay simulation unit, which are respectively used to analogize the phase time delay generated by the input port level detection circuit and the Q port data sampling and drive output circuit, and compensate for the phase difference generated by the two. At the same time, the power supply parameters of the clock input port level detection delay simulation unit remain consistent with the power supply of the input port level detection, and the power supply parameters of the Q port data output drive delay simulation unit remain consistent with the power supply of the Q port data sampling and drive output circuit. In addition, an adjustable delay unit circuit is used to compensate for the time delay caused by large parasitic resistance and parasitic capacitance generated by long metal traces in the layout.

Methods and apparatus for joint scheduling and beam design in a phase-time array (JPTA). In another embodiment, a method for operating a base station (BS) is provided. The method includes identifying a set of user equipments (UEs) to schedule, a plurality of resource blocks (RBs), and a UE beam map. The UE beam mapping maps one or more of the plurality of beams to one or more UEs of the set of UEs. The method also includes, for a UE in the set of UEs, allocating one or more RBs to the UE from the plurality of RBs based on the UE beam map and the beam gain of the one or more RBs in the direction of the UE. The method also includes determining a JPTA beam for the UE. The method also includes transmitting scheduling information indicating the allocated one or more RBs and the determined one or more JPTA beams.

The application discloses a phase compensation method of a multifunctional electric power digital display instrument, relates to the technical field of phase compensation, and is used for improving the incompatible problems of phase differences of various detection circuits in the multifunctional electric power digital display instrument, and comprises the following steps: detecting a correction environment, obtaining a normal power frequency period of a reference signal, setting a power frequency locking experiment in the correction environment to determine the power frequency of the reference signal, calculating the power frequency period according to the power frequency of the reference signal, setting the number of oversampling, calculating a sampling interval by using a geometric mean method according to the power frequency period and the number of oversampling, calculating a sampling point interval difference after the sampling interval is determined, obtaining historical data, comprehensively using the historical data and the sampling point interval difference to select direct compensation or time delay adjustment by using fuzzy reasoning, detecting channel noise when the time delay adjustment is selected, collecting phase differences of various channels, converting the phase differences into phase time differences, and completing phase compensation according to the phase time differences.

The embodiment of the present application provides a multi-phase time synchronization method, system, device and terminal equipment. The multi-phase time synchronization system includes a reference time synchronizer, a timestamp generator and at least one task node. The reference time synchronizer is used to obtain the reference time in real time through the Beidou timing system and publish the reference time to at least one task node. The timestamp generator is used to receive the clock frequency generated by the high-stability clock generator and generate a multi-phase timing signal based on the clock frequency. At least one task node is used to obtain the corresponding absolute time based on the reference time and the multi-phase timing signal, and perform time synchronization according to the absolute time. In this application, not only can the time synchronization accuracy of each task node be improved, but also the time accuracy in different temperature environments can be made more accurate and reliable.

Method for predicting the remaining duration of a signal aspect of at least one signal group (303, 305) of a traffic signal system (301), wherein the traffic signal system (301) is controlled based on a signal program which specifies several phases (401, 407) for a cycle time and a separate phase permission range for each of the several phases (401, 407), wherein for immediately successive phases (401, 407) the associated phase permission ranges (503, 505) seamlessly connect or overlap, so that the phase permission ranges (503, 505) cover the entire cycle time (607), wherein a phase transition between two immediately successive phases (401, 407) is specified by means of a phase sequence plan (405), wherein the signal aspect is specified by a currently running phase (401) of the signal program.comprising the following steps: Determining (101) a minimum phase remaining time and a maximum phase remaining time of the currently running phase (401) for a current cycle time point (717) of the cycle time (607) based on the phase permission range (503) of the currently running phase (401) and on the phase permission range (505) of the phase (407) that immediately follows the currently running phase (401); Determining (103) a minimum and a maximum remaining time of the signal aspect of the signal group (303, 305) for the current cycle time point (717) based on the minimum phase remaining time, on the maximum phase remaining time and on the respective phase sequence plan (405) that specifies the phase transition between the currently running phase (401) and the immediately following phase (407), wherein, in the case that the respective phase sequence plan (405),which specifies the phase transition between the currently running phase (401) and the immediately following phase (407) for the signal group (303, 305), does not specify a change in the signal aspect, successively searches for a change in the signal aspect of the signal group (303, 305) in phase sequence plans that follow the respective phase sequence plan (405) until a change is found in one of the following phase sequence plans, whereby the steps of determining (101) a minimum remaining phase duration and a maximum remaining phase duration for the current cycle time point (717) of the cycle time (607) are repeated for each of the phases until the signal aspect changes, wherein a first sum of all determined minimum remaining phase durations is calculated and wherein a second sum of all determined maximum remaining phase durations is calculated, wherein the minimum remaining phase duration of the signal aspect of the signal group (303,305) is determined based on the first sum and on the phase sequence plan in which the change of the signal aspect was found, and wherein the maximum remaining duration of the signal aspect of the signal group (303, 305) is determined based on the second sum and on the phase sequence plan in which the change of the signal aspect was found.

The present invention discloses a bus priority signal control method based on a mobile bus phase time window. First, the bus time window is calculated in combination with bus speed fluctuations and theoretical arrival time points; secondly, a bus priority strategy set is established with the goal of covering the bus arrival time window with the green light time of the bus phase, without changing the bus phase duration and the overall phase structure. This signal adjustment method is a bus priority strategy that moves the bus phase time window based on the prediction of the bus arrival time to adapt to the public transportation demand; finally, bus signal priority control is implemented based on the strategy group. The present invention can minimize the encroachment of the green light time of other phases due to bus priority, avoid the failure of bus priority caused by errors in arrival time, excessive extension of bus phase duration and adjustment of the overall phase structure, and improve the overall traffic efficiency of the intersection.

The invention provides a data analysis method and device, a storage medium and a program product. The method comprises: based on a to-be-analyzed time period of a specified service, determining a first time period and a second time period in historical reference time periods of the to-be-analyzed time period, the historical reference time periods including a plurality of periods, the first time period including an in-phase time period of the to-be-analyzed time period in each period, and the second time period including an in-phase time period; the second time period is other time periods except the first time period in the historical reference time periods; obtaining time sequence service data of the specified service in a first time period according to a first obtaining mode to obtain first time sequence service data, and obtaining time sequence service data of the specified service in a second time period according to a second obtaining mode to obtain second time sequence service data, the data acquisition interval of the first acquisition mode is smaller than the data acquisition interval of the second acquisition mode; and performing data analysis based on the obtained time sequence business data to obtain an analysis result corresponding to the to-be-analyzed time period.

The invention discloses a phase compensation method of a multifunctional electric power digital display instrument, relates to the technical field of phase compensation, and aims to solve the problem that phase differences of various detection circuits in the multifunctional electric power digital display instrument are incompatible. Setting a power frequency locking experiment in a correction environment to determine the power frequency of a reference signal, calculating a power frequency period according to the power frequency of the reference signal, setting an oversampling frequency, calculating a sampling interval by using a geometric average method according to the power frequency period and the oversampling frequency, determining the sampling interval, calculating a sampling point interval difference, and obtaining historical data; selecting direct compensation or time delay adjustment by using fuzzy reasoning according to the historical data and the sampling point interval difference, detecting channel noise, collecting the phase difference of each channel, converting the phase difference into a phase time difference, and completing phase compensation according to the phase time difference when the time delay adjustment is selected.

This invention discloses a multi-stage time synchronization method for a structural health monitoring array, comprising: preprocessing a floor acceleration signal with unknown time delay; calculating the initial delay of the floor acceleration signal based on cross-correlation; calculating the residual time delay of the floor acceleration signal based on wave propagation constraints; calculating the residual time delay of the floor acceleration signal based on cross-spectral phase; reconstructing the synchronized floor acceleration signal using the initial delay, residual time delay, and residual time delay; calculating the displacement response through integration; and outputting the inter-story displacement. This invention divides the synchronization process into three sequential stages: the first stage rapidly reduces the large time delay to the order of several vibration periods; the second stage further refines the process, controlling the residual time delay within one period; and the third stage utilizes phase information to achieve high-precision synchronization while limiting the frequency range to avoid the influence of high-frequency noise.

The invention relates to a method for regulating a unit for separating a gas stream, having P adsorbers, where P≥2, each following a PSA-type adsorption cycle with a phase time shift, the method involving the steps of operating the unit according to the nominal cycle when the required flow rate is equal to a nominal flow rate or optionally when the required flow rate is higher than the nominal flow rate, and operating the unit according to the reduced cycle when the required flow rate is lower than or equal to a predetermined flow rate, the predetermined flow rate being lower than the nominal flow rate.

The invention discloses a frequency agility frequency synthesizer system capable of keeping phase consistency, relates to the technical field of frequency synthesis, and forcibly constrains an originally asynchronous and random frequency updating request to a determined time node generated by a frequency dividing circuit. And the frequency of the synchronous trigger signal becomes a common divisor of all preset output frequencies, namely the output frequency and the trigger frequency are in an integral multiple relationship. No matter when the system sends out a frequency hopping instruction, the actual frequency switching action is always standardized at the determined zero-phase time points, so that the phase randomness introduced due to uncertain instruction arrival time is eliminated, the phases of output signals are strictly consistent in any two processes of hopping from the same frequency to the same frequency, and the frequency hopping efficiency is improved. And phase maintenance and repeatability are realized.