Time-to-digital conversion circuit and correlation method thereof

Abstract

The invention provides a time-to-digital conversion circuit, which comprises a first delay circuit, a second delay circuit, a first counter, a second counter and a comparator, wherein the first delay circuit is provided with a first delay level and used for delaying a first input signal to generate a first output signal; the second delay circuit is provided with a second delay level and used for delaying a second input signal to generate a second output signal; the first counter is used for counting the first output signal to generate a first counting value; the second counter is used for counting the second output signal to generate a second counting value; the comparator is used for comparing the first counting value with the second counting value to generate a comparison result signal; the first delay level has larger delay quantity than the second delay level; the first counter begins to count earlier compared with the second counter; and when the second counting value is within a preset range comprising the first counting value, the comparator outputs the comparison result signal.

Description

Technical field [0001] The present invention relates to a time-to-digital conversion circuit, and more particularly to a time-to-digital conversion circuit that uses a delay circuit to generate a periodic delay signal. Background technique [0002] Generally speaking, a time to digital conversion circuit (Time to Digital Converting, TDC) is used to measure the degree of delay of a signal, so as to convert the degree of delay of the signal into the amount of delay of the actual delay stage, that is, to determine the degree of delay of the signal. The number of delay stages is expressed. The old method is to send the first signal and the second signal to the first delay circuit and the second delay circuit respectively, where the first signal (usually the signal to be measured) is sent in longer than the second signal (usually the signal to be measured). The known reference signal) is early, but the delay amount of the delay stage of the first delay circuit is larger than the delay...

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Problems solved by technology

[0003] However, in such an approach, it is often necessary to use the entire delay circuit, so the circuit will have a larger area

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