142 results about "Asynchronous sampling" patented technology

A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A / D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A / D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection. When the RRO address mark is found, the corresponding best phase corresponds to either asynchronous sampled values or interpolated samples that are subsequently selected for RRO data detection, termed best samples. Once the best phase is selected, the RRO data detector uses that information along with RRO encoding constraints to decode the encoded RRO data from the best samples.

A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

Methods and apparatus are provided for decimated interpolated clock / data recovery (ICDR) to perform asynchronous sampling of a received signal. A received signal is converted to a plurality of digital samples at a downsampled rate that is lower than a rate of the received signal. The plurality of digital samples are interpolated using a plurality of parallel interpolation filters operating at the downsampled rate. An output of each parallel interpolation filter is applied to a corresponding data detector operating at the downsampled rate to generate digital data. An estimate of a timing error is generated based on the digital data. The timing error values are processed to generate an interpolation phase value that is applied to the parallel interpolation filters. A recovered clock is optionally generated, having edges corresponding to a desired synchronous sampling period.

Asynchronous sampling rate converter with input / output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control frequency ratio estimation.

An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses. A coefficient calculation circuit calculates filter coefficients for the interpolation and resampling circuit in response to the difference signal.

Methods for sample rate conversion are provided that use a polynomial interpolator with minimax stopband attenuation. A method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a discrete polyphase index m. Another method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a continuous polyphase index τ. In these methods, an output time index is mapped to an input sample index and the polyphase index, the polynomial coefficients of a polyphase filter are computed using the polyphase index, and the polyphase filter is applied to an input sample at the input sample index to generate the output sample at the output time index.

The waveform deterioration detection range is broadened and multi bit rates can be handled. A chromatic dispersion compensator (or polarization mode dispersion compensator) (102) receives a waveform-deteriorated NRZ optical signal entered through an input fiber (101) and compensates it. On the other hand, an optical detector (106) receives part of output light and a sampling circuit (A / D converter) (107) performs asynchronous sampling of received waveform intensity. A control circuit (110) calculates the nth even moment (n is 4 or more) from an obtained waveform amplitude histogram and performs control to minimize its value.

The invention discloses a method for calculating the dielectric loss angle of a compatible insulating device in the technical field of monitoring. According to the technical scheme, firstly, a Blackman self-convolution window is constructed, current and voltage signals of a device to be detected are collected, and discrete sampling is performed on the current and voltage signals; secondly, windowing truncation is performed on a discrete signal sequence with the constructed Blackman self-convolution window, and a discrete spectrum function of discrete signals after the windowing truncation is obtained; thirdly, the discrete spectrum function of the discrete signals after the windowing truncation is analyzed, and a main lobe width and side lobe characteristics are obtained; finally, voltage and current fundamental wave signal phase angles are solved with the four spectral line interpolation amendment theory, and therefore the dielectric loss angle is solved. According to the method for calculating the dielectric loss angle of the compatible insulating device, the extremely good spectrum leakage restraining effect of the Blackman self-convolution window is used, frequency spectrum correction is performed with the four spectral line interpolation, dielectric loss angle measuring errors based on the FFT theory under asynchronous sampling are avoided, the measuring precision is high, and requirements for hardware are low.

The invention discloses a dual-loop DLL-based three-segment type high-precision time-to-digital conversion method and circuit. According to a measured time segment, a high-middle-low combined segmental type quantization method is adopted. A high-segment bit counting type quantizer in three-segment type TDC (time-to-digital conversion) is driven by a high-frequency stabilizing clock which is inputted from the outside, so that a wide-range stable distance measuring range can be realized; a middle-segment bit TDC is formed by a first DLL voltage controlled delay chain; high-segment bit subdivision can be realized through an asynchronous sampling mode, and repeatable uniform phase distinguishing can be accomplished in a stable clock period; a phase position at a termination time point is decoded, so that a middle-segment quantization function can be accomplished; and according to quantization errors generated by time-to-digital conversion in a middle-segment bit, error time is extracted, a low-segment bit accomplishes further quantization processing, and therefore, higher measurement precision can be realized.

A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

The invention relates to an asynchronous sample rate converter (ASRC) for the conversion of the sample rate of digital data such as audio data or video data. In the case of high over-sampling or sub-sampling factors an ASRC becomes quite complex. It is an object of the invention to provide an ASRC with a simplified design for such purposes. It is suggested to use an ASRC which has a n-tap polyphase filter, whereby a computational entity performs a polynomial computation of the filter coefficients. The attenuation at the notch frequencies is best when using a Parzen window or a quadratic window.

Systems and methods for asynchronous sample rate conversion are provided that allow time-varying arbitrary sample ratios. An uncorrected ratio between two arbitrary sample rates is corrected and subsequently used to perform an efficient sample rate conversion on the samples in a data stream. Coefficients of a (polyphase) finite impulse response filter are interpolated based on a current time register value. Additional computational efficiency (and a smaller finite impulse response filter) may be used due to oversampling the input signal to the finite impulse response filter.

The invention relates to a harmonic analysis method based on asynchronous sampling, belonging to the field of signal harmonic detection technique. The method comprises the steps as follows: 1) a plurality of prearranged weight coefficients corresponding to signal frequencies one-to-one are sequentially memorized in a memory; 2) the harmonics are sampled under a constant sampling period; a sampling signal is output to a digital signal processor after A / D conversion; 3) the digital signal processor processes digital signals which are converted by multi-path A / D converters, and according to the frequencies, the positions of the weight coefficients needed to be invoked in the memory are determined; 4) in the digital signal processor, corresponding weight coefficients invoked in the memory is multiplied by the input digital signals, subsequently, FFT processing is carried out; and 5) the FFT-processed result is displayed or printed. The method overcomes the synchronous difference problem of the harmonic analysis, obtains real-time harmonic analysis signals with high precision, and can be applied to the signals in the fields such as machines, power, information, geology, hydrology and the like so as to carry out the harmonic analysis.

In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

The invention discloses a signal harmonic spectral analysis method and system based on a Hanning product window. The method includes the steps that discrete signals are windowed through the Hanning product window, and FFT is conducted on the windowed signals and the Hanning product window; actual fundamental frequency and the amplitude and the phases of sub-harmonics are acquired according to a signal spectrogram obtained after FFT and the Hanning product window obtained after FFT. The Hanning product window is combined with FFT, and harmonic analysis with extremely high accuracy can be achieved in an asynchronous sampling state; meanwhile, the signal harmonic analysis method and system further have the advantages of being small in calculated amount, short in consumed time, high in practicability and the like.

An optical signal quality monitoring apparatus includes an optical detector for directly receiving an optical signal modulated in an optical path and converting the optical signal to an electric signal, an asynchronous sampling unit for asynchronously sampling the electric signal of the optical detector at a reduced speed, and a digital signal processor for monitoring an optical signal quality by finding a synchronized amplitude histogram of data sampled in the asynchronous sampling unit. An optical signal quality monitoring method includes (a) a step of allowing an optical detector to directly receive a modulated optical signal and to convert the optical signal to an electric signal; (b) a step of allowing an asynchronous sampling unit to asynchronously sample the electric signal; and (c) a step of allowing a digital signal processor to monitor an optical signal quality by generating a synchronized amplitude histogram of sampled data.

The invention discloses a signal harmonic analysis method and system based on a Hamming product window. The method includes the steps that discrete signals are windowed through the Hamming product window, and FFT is conducted on the windowed signals and the Hamming product window; actual fundamental frequency and the amplitude and the phases of sub-harmonics are acquired according to a signal spectrogram obtained after FFT and the Hamming product window obtained after FFT. The Hamming product window is combined with FFT, and harmonic analysis with extremely high accuracy can be achieved in an asynchronous sampling state; meanwhile, the signal harmonic analysis method and system further have the advantages of being small in calculated amount, short in consumed time, high in practicability and the like.

Methods and apparatus are provided for decimated interpolated clock / data recovery (ICDR) to perform asynchronous sampling of a received signal. A received signal is converted to a plurality of digital samples at a downsampled rate that is lower than a rate of the received signal. The plurality of digital samples are interpolated using a plurality of parallel interpolation filters operating at the downsampled rate. An output of each parallel interpolation filter is applied to a corresponding data detector operating at the downsampled rate to generate digital data. An estimate of a timing error is generated based on the digital data. The timing error values are processed to generate an interpolation phase value that is applied to the parallel interpolation filters. A recovered clock is optionally generated, having edges corresponding to a desired synchronous sampling period.

The invention discloses a realtime high-accuracy non-sinusoidal periodic signal detection method, which comprises the following steps of: sampling non-sinusoidal periodic signals to be detected; calculating frequency, amplitude and phase of fundamental wave and harmonic of each order by using neural network based on triangular base function; and correcting the frequency of the fundamental wave of the non-sinusoidal periodic signal calculated by the neutral network by using windowed interpolation algorithm. By improving the neural network algorithm, the invention can execute high-accuracy analysis of frequency of the fundamental wave and amplitudes and phases of the fundamental wave and the harmonic of each order for asynchronous sampling and non-integer-period truncation, and high-accuracy harmonic analysis result of non-sinusoidal periodical signal can be obtained when the neutral network is convergent. The invention has the advantages of high speed, realtime operation, high accuracy, etc., and has wide application prospect in fields of mechanical engineering, motor testing, electric system stability analysis, signal processing, instrument and apparatus, industrial control, etc.

Data signals received in an integrated circuit are coupled to a receiver and to an on-chip data acquisition system which takes measurement samples of the data signal in response to a measurement request. The measurement request is synchronized with an asynchronous sample clock signal generating a capture signal and a counter reset signal. A counter measures the number of sample clock cycles between measurement requests. On receipt of a measurement request, the capture signal triggers the storage, as capture data, the preset number of cycles in the counter and the measurement samples in a register. The counter is synchronously reset and the capture data is sent to off-chip storage. The off-chip storage stores an arbitrary amount of capture data and the area on-chip is greatly reduced for the on-chip data acquisition. An off-chip analysis is used to construct an effective time base for the capture data for signal analysis

The invention provides a method for acquiring the networking transmission network time delay of the sampling value of an intelligent transformer substation. The sampling value is transmitted in the form of a message. The method comprises the following steps: initializing the filling value of a message reservation field into 0; allowing the message to enter a switch for performing network transmission, and recording an entrance time point at which the message enters the current switch and a transmission time point at which the message leaves the current switch respectively; acquiring the retention time of the message in the current switch, overlapping the retention time with data in the reservation field, and replacing the data in the reservation field; judging whether the message arrives at a target position or not, and if so, carrying out a next step; otherwise, searching for a next switch and returning; and acquiring data in the reservation field to obtain a total network time delay value. The invention further relates to a device for implementing the method. The method and the device for acquiring the networking transmission network time delay of the sampling value of the intelligent transformer substation have the beneficial effects that networking transmission can be performed in asynchronous sampling, and the network time delay can be determined.

A method and a system for measuring an optical asynchronous sample signal. The system for measuring an optical asynchronous sampling signal comprises a pulsed optical source capable of emitting two optical pulse sequences with different repetition frequencies, a signal optical path, a reference optical path, and a detection device. Since the optical asynchronous sampling signal can be measured by merely using one pulsed optical source, the complexity and cost of the system are reduced. A multi-frequency optical comb system using the pulsed optical source and a method for implementing the multi-frequency optical comb are further disclosed.

The invention discloses a method for extracting power grid voltage flicker envelope parameters. According to the method, power grid voltage flicker waveforms are sampled at a constant sampling frequency, a flicker envelope amplitude modulated wave component is obtained through energy calculation of an improved Teager energy operator, a cosine window is added to conduct Chirp-Z conversion, the flicker envelope amplitude modulated wave frequency and a correction factor of an amplitude modulated wave amplitude value are extracted by improving the Chirp-Z conversion, and the flicker envelope amplitude modulated wave amplitude value is corrected through the correction factor and accurately obtained; through the combination of the improvement on the energy operator and the improvement on the Chirp-Z conversion, the energy operator is improved, the flicker envelope demodulation calculation process by the energy operator is improved, the noise resistance is improved; by improving the Chirp-Z conversion, the flicker frequency analysis range is flexible and adjustable, and frequency spectrum leakage generated under the condition of asynchronous sampling and errors caused by a picket fence effect are effectively avoided; the correction factor of the amplitude modulated wave amplitude value reduces the errors caused by the energy operator, and the power grid voltage flicker envelope parameters can be accurately measured in real time.

A method and system to economically monitor an optical OOK signal that can detect perceptible changes in signal quality and identify the type of optical impairment causing the change. The invention requires a new and novel combination of known techniques to create an eye diagram of the transmitted pulse in a wavelength division multiplexing systems and then removing the noise from the eye diagram. Economy of operation is achieve by using asynchronous sampling techniques for generating the eye diagram. The resulting “cleaner” eye diagram is then analyzed to identify any changes in performance. In the preferred embodiment, the analysis is conducted on histograms generated from eye diagram, the histograms are computed at a number of points across the optical signal pulse period.

The sample rate of a digital signal is converted by a digital simulation of an analog filter. The simulation can update the states of complex poles in the analog filter at arbitrary times using different techniques. One technique updates the states at variable rates. Other techniques update the states at a fixed rate in response to values of input or output samples that are modified to account for offsets between the times of the samples and the times the states are updated. The states may be updated by using interpolations of complex exponential functions. Values of the complex exponential functions may be obtained from a product of values obtained from multiple lookup tables.

The invention discloses an adjacent harmonic and inter-harmonic separation and measurement method under an IEC (international electrotechnical commission) framework. The method includes the following steps: firstly, performing discrete sampling on a power grid signal; secondly, performing ten-cycle Hanning window addition DFT / FFT (discrete Fourier transform / fast Fourier transform) spectral transformation on a sampling value according to IEC standards so as to obtain a spectrum; thirdly, multiplying the spectrum by rotary phase factors to obtain a new spectrum; fourthly, solving a vector sum of neighboring spectral lines of the new spectrum so as to offset sidelobe interference of rest components on the new spectrum, and solving corresponding frequency, a frequency deviation value and amplitude phase via a spectral line phase cancellation interpolation method; fifthly, rejecting spectrum leakage values of a fundamental component and the rest components at spectral line attention positions on a frequency domain; sixthly, solving a harmonic spectrum value to obtain parameters of h subharmonics, and solving parameters of inter-harmonics adjacent to the h subharmonics. By the method, the problem that the parameters of the two adjacent harmonics and inter-harmonics cannot be measured accurately during limited data asynchronous sampling is solved.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

This invention relates to the security of the FPGA of the SRAM technology characterizing in adding an asynchronous sampling step in the FPGA circuit to let a cryptographic key selection state set select the FPGA cryptographic key from an internal list of the FPGA randomly, at the same time, the cryptographic key transfer instruction sent to CPLD is a random sequence, besides, M sequence de-cipher and cipher circuit are added in the FPGA and CPLD, so the cryptographic keys from CPLD to FPGA should be ciphered by the M sequence to increase the anti-attack ability of the system and the transfer of cryptographic state increases difficulty in recognization and interpretation since a cribber should master numbers of state machines and their ruleless transfer modes.

A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A / D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A / D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection. When the RRO address mark is found, the corresponding best phase corresponds to either asynchronous sampled values or interpolated samples that are subsequently selected for RRO data detection, termed best samples. Once the best phase is selected, the RRO data detector uses that information along with RRO encoding constraints to decode the encoded RRO data from the best samples.