System for improving SRAM process EPGA design safety by asynchronous circuit

Abstract

This invention relates to the security of the FPGA of the SRAM technology characterizing in adding an asynchronous sampling step in the FPGA circuit to let a cryptographic key selection state set select the FPGA cryptographic key from an internal list of the FPGA randomly, at the same time, the cryptographic key transfer instruction sent to CPLD is a random sequence, besides, M sequence de-cipher and cipher circuit are added in the FPGA and CPLD, so the cryptographic keys from CPLD to FPGA should be ciphered by the M sequence to increase the anti-attack ability of the system and the transfer of cryptographic state increases difficulty in recognization and interpretation since a cribber should master numbers of state machines and their ruleless transfer modes.

Description

technical field [0001] The invention relates to the design security of the SRAM process FPGA, and is an effective means for protecting the internal design content of the FPGA from plagiarism. Background technique [0002] With the improvement of FPGA capacity, performance and reliability, and its large-scale application in consumer electronics, automotive electronics and other fields, the safety of FPGA design has attracted more and more attention. Due to its advantages in technology, SRAM process FPGA has become the mainstream of current FPGA. However, due to the volatility of SRAM, the configuration information in the chip will be lost after power off, so it needs to be reconfigured every time the system is powered on. This allows plagiarists to obtain the configuration data stream of the FPGA by sampling the configuration data pins of the FPGA, and realize the cloning of the internal design circuit of the FPGA. [0003] The industry and academia have proposed various so...

AI Technical Summary

Problems solved by technology

The disadvantage of this solution is that the external battery not only increases the cost, but also reduces the stability of the system

Tom Kean proposed an improvement to Xilinx's method, which does not require an external battery, but requires writing a non-volatile key in each FPGA with a non-SRAM process

The disadvantage of this method is that it does not match the traditional FPGA production process and is not suitable for mass production

There are still many schemes to improve the security of FPGA design using encryption algorithms, all of which are repairs to the above two methods. In general, the key storage of these schemes requires special support, either using an external battery or changing the existing FPGA production process

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