All-digital phase-locked ring applicable to video signal processing

Abstract

The invention discloses an all-digital phase-locked ring applicable to video signal processing, comprising an analog-to-digital conversion circuit ADC, an automatic gain control circuit AGC, a digital low-pass filter DLPF, a synchronous header split circuit, a frequency detector FD, a time-to-digital conversion circuit TDC, a coarse tuning filter, a phase detector PD, a fine tuning filter, a summator, a digital-controlled oscillator and a pixel frequency divider circuit. The phase detector, the time-to-digital conversion circuit, the coarse tuning filter, the digital-controlled oscillator and the pixel frequency divider circuit constitute a frequency locking loop circuit, and the locking process of the all-digital phase-locked ring is accelerated. The analog-to-digital conversion circuit, the automatic gain control circuit, the digital low-pass filter, the frequency detector, the phase detector, the fine tuning filter, the digital-controlled oscillator and the pixel frequency divider circuit constitute a phase locking loop circuit, and the phase locking loop circuit is used for accurately locking the phase of a synchronous header in an analogue video signal.

Description

technical field [0001] The invention mainly relates to the field of integrated circuit design related to analog video signal processing, in particular to an all-digital phase-locked loop applied to video signal processing. Background technique [0002] For the processing of the analog video signal, usually the analog video signal is firstly sampled by an ADC to obtain a digital video signal, and then the video signal is processed by a relevant digital circuit. For a video signal of a specific system, the number of pixels in one line is fixed, and the frequency of the sending video signal is usually different from the frequency of the receiving video signal, which is obtained under the condition of sampling the analog video signal with a fixed clock The number of pixels of each row of video signals will be different, and the video signal will introduce jitter during transmission, which will cause the relative sampling position of the pixels of each row of video signal to devi...

AI Technical Summary

Problems solved by technology

But no matter which way the horizontal synchronization phase-locked loop is implemented, the horizontal synchronization signal is required as a reference clock, and the phase of the reference clock needs to be independent of the phase of the horizontal synchronization phase-locked loop output clock, which usually requires an analog circuit to separate the analog The synchronization information in the video signal obtains the horizontal synchronization signal, but the synchronization signal cannot be separated from the sampled digital video signal

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