A layout design method for improving the ESD protection capability of an interdigital structure type device is characterized in that on the basis of a traditional interdigital type ESD protection device, the length of a drain region interdigital is increased at the center of an interdigital structure, and according to the fact that the total length of a gate structure and a source structure is not changed, the farther the distance from the center of the interdigital structure is, the farther the distance from the center of the interdigital structure is; and designing the interdigital length of the drain region according to the principle that the interdigital length of the drain region is smaller. Finally, under the condition that the total length of the gate and source structures is not changed and the area is the same, the ESD capability is higher; when the ESD capacity is the same, the area is smaller; the influence of current heterogeneity during ESD protection of the interdigital structure type device is relieved, compared with a traditional interdigital structure device, the MOS device using the method is better in ESD protection capacity, higher in current discharge capacity and higher in reliability, layout modification only needs to be conducted on a chip, and the manufacturing cost is reduced. The performance of the interdigital structure can be improved without influencing the basic parameters of the device, and the ESD protection capability, the reliability and the electrostatic discharge capability of the interdigital structure type device are improved.