Layout design method for improving ESD (Electro-Static Discharge) protection capability of interdigital structure type device

Abstract

A layout design method for improving the ESD protection capability of an interdigital structure type device is characterized in that on the basis of a traditional interdigital type ESD protection device, the length of a drain region interdigital is increased at the center of an interdigital structure, and according to the fact that the total length of a gate structure and a source structure is not changed, the farther the distance from the center of the interdigital structure is, the farther the distance from the center of the interdigital structure is; and designing the interdigital length of the drain region according to the principle that the interdigital length of the drain region is smaller. Finally, under the condition that the total length of the gate and source structures is not changed and the area is the same, the ESD capability is higher; when the ESD capacity is the same, the area is smaller; the influence of current heterogeneity during ESD protection of the interdigital structure type device is relieved, compared with a traditional interdigital structure device, the MOS device using the method is better in ESD protection capacity, higher in current discharge capacity and higher in reliability, layout modification only needs to be conducted on a chip, and the manufacturing cost is reduced. The performance of the interdigital structure can be improved without influencing the basic parameters of the device, and the ESD protection capability, the reliability and the electrostatic discharge capability of the interdigital structure type device are improved.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a layout design method for improving the ESD protection capability of an interdigitated device. Background technique [0002] With the development of the manufacturing process of integrated circuits, the feature size of CMOS technology continues to shrink, and the ability of transistors to withstand high voltage and high current continues to decrease. CMOS integrated circuits are more susceptible to failure due to electrostatic shock, resulting in a decline in product reliability. [0003] Static electricity is ubiquitous in the process of chip manufacturing, packaging, testing and use. The accumulated static charge is released in nanoseconds to microseconds with a current of several amperes or tens of amperes. The instantaneous power is as high as hundreds of kilowatts, and the discharge energy It can reach millijoules, and the destruction intensity of the chip is ...

AI Technical Summary

Problems solved by technology

However, high-voltage LDMOS devices exhibit greater snapback than low-voltage MOS devices, and generally the multi-finger uniform trigger condition with failure voltage greater than the trigger voltage cannot be satisfied, and it is more difficult to uniformly trigger than low-voltage multi-finger devices, which directly affects the on-chip of high-voltage circuits. ESD protection ability

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