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Electrostatic discharge protection device

An electrostatic discharge and protection device technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problem of the decline of the ESD protection ability of GGNMOS

Active Publication Date: 2020-06-12
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But this will reduce the ESD protection abilit

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Embodiment Construction

[0019] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It wil...

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Abstract

The invention relates to an electrostatic discharge protection device which comprises a first GGNMOS device and a second GGNMOS device which are adjacent to each other, and each of the first GGNMOS device and the second GGNMOS device comprises a well region; a first conductive type doped region which is arranged in the well region and comprises a drain region and a source region; and agrid electrode which is arranged above the area between the drain electrode area and the source electrode area; each of the first GGNMOS device and the second GGNMOS device comprises a plurality of GGNMOS transistors, and each GGNMOS transistor comprises a grid electrode, a source electrode region on one side of the grid electrode and a drain electrode region on the other side of the grid electrode; the GGNMOS transistor closest to the two GGNMOS devices is the GGNMOS transistor with the largest DCG, and the DCG is the distance from a drain electrode contact hole of the GGNMOS transistor to a grid electrode of the GGNMOS transistor. According to the invention, the DCG of the nearest GGNMOS transistor is enlarged, better ESD protection capability can be provided for the extreme condition, and the ESD performance between the input port and the output port is optimized. The area utilization rate of the wafer is higher, and the manufacturing cost is reduced.

Description

technical field [0001] The invention relates to electrostatic discharge (ESD) protection, in particular to an electrostatic discharge protection device. Background technique [0002] GGNMOS (Gate Groud NMOS, that is, gate-grounded NMOS) is a common CMOS ESD protection device. When more pins are drawn out from a chip, more GGNMOS protection ports are used, which causes GGNMOS to occupy a larger wafer area. [0003] In order to save more wafer area, one solution is to remove the N well isolated between GGNMOS, so that GGNMOS can share the Psub lead-out area, saving more area. But this will reduce the ESD protection ability of GGNMOS due to the parasitic NPN turning on. Contents of the invention [0004] Based on this, it is necessary to provide an electrostatic discharge protection device with better ESD protection capability. [0005] An electrostatic discharge protection device, including a first GGNMOS device and a second GGNMOS device adjacent to each other, the first...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0266
Inventor 汪广羊
Owner CSMC TECH FAB2 CO LTD
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