Cell structure and manufacturing method thereof

A manufacturing method and cell technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of complex formation and increased cost, and achieve design flexibility, cost reduction, and improvement of ESD capabilities. Effect

Active Publication Date: 2015-04-29
HANGZHOU SILAN MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the formation of these ESD protection components is relatively complicated, and additional masks are required, which increases the cost while improving the ESD capability
[0004] Therefore, it is necessary to propose a new power semiconductor device to solve the problem that the ESD protection component in the prior art needs to add an additional mask to improve the anti-ESD capability, and the relatively complicated problem is formed.

Method used

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  • Cell structure and manufacturing method thereof
  • Cell structure and manufacturing method thereof
  • Cell structure and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0049] Figure 3 to Figure 5 It shows that the present invention provides a power semiconductor device with anti-static discharge capability, and the gate terminal is connected in series with strip resistors to form a circular array layout structure of the gate.

[0050] Such as Figure 3 to Figure 5 As shown, the steps for forming each of the cells 8 are as follows: provide an epitaxial layer (not shown in the figure, please refer to Figure 2A to Figure 2C In the mark 6); form a second-type lightly doped region in the epitaxial layer (not shown in the figure, please refer to Figure 2A to Figure 2C Mark 5 in the above); on the epitaxial layer, a gate dielectric layer is sequentially formed from bottom to top (not shown in the figure, please refer to Figure 2A to Figure 2C Mark 7) and the first polysilicon strip 4; etch the first polysilicon strip 4 and the gate dielectric layer to expose the second-type lightly doped region; in the second-type lightly doped A first type ...

Embodiment 2

[0057] Figure 8 to Figure 9 Shown is the circular array layout structure of the source terminal of the power semiconductor device with anti-static discharge capability of the present invention, which is connected in series with strip resistors to form the source.

[0058] Such as Figure 8 and 9 As shown, the steps for forming each of the cells 8 are as follows: provide an epitaxial layer (not shown in the figure, please refer to Figure 2A to Figure 2C In the mark 6); form a second-type lightly doped region in the epitaxial layer (not shown in the figure, please refer to Figure 2A to Figure 2C Mark 5 in the above); on the epitaxial layer, a gate dielectric layer is sequentially formed from bottom to top (not shown in the figure, please refer to Figure 2A to Figure 2C Mark 7) and the first polysilicon strip 4; etch the first polysilicon strip 4 and the gate dielectric layer to expose the second-type lightly doped region; in the second-type lightly doped A first type hea...

Embodiment 3

[0068] Figure 12 The difference between the illustrated embodiment and the first and second embodiments is to provide a circular array layout structure in which the gate terminal and the source terminal of the power semiconductor device with anti-static discharge capability are simultaneously connected in series with resistors to form the gate and source.

[0069] In this embodiment, the changed embodiment 1 can be combined with the layout structure of embodiment 2 to form Figure 12 . The content of the changes in the first embodiment is as follows: a first port 1' is provided on the second polysilicon strip 4', and a second port 1' is provided on the second polysilicon strip 4' other than the first port 1' The gate 1 is formed, and the second polysilicon strip 4 ′ is a resistor R1 connected to the first port, and the first port 1 ′ has no direct electrical connection with the gate 1 . Then, the size of the resistor R1 connected in series with the gate terminal can be adju...

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PUM

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Abstract

The invention provides a cell structure. A plurality of cells are arranged to form a cell array structure so as to form a power semiconductor device with three ports, any one or more of the three ports are respectively connected with a resistor, each cell comprises an epitaxial layer; a second type light doped region is formed in the epitaxial layer; a first type heavy doped region and a second type heavy doped region are respectively formed in the second light doped region; heavy doped region short circuit holes are formed in the first heavy doped region and the second heavy doped region; gate medium dielectric layers are formed on the surfaces of the epitaxial layer, the second light doped region closely adjacent to the epitaxial layer and a part of the first heavy doped region closely adjacent to the second light doped region; first polycrystalline silicon strips are formed on the gate medium dielectric layers; and regions surrounded by the first heavy doped regions and the heavy doped region short circuit holes of the all cells in the second light doped region are resistors which are connected with a second port, wherein the serial resistors can improve the ESD (electronic static discharge) capability and the cell structure is slightly adjusted so as to be capable of meeting requirements of ESD with various grades.

Description

technical field [0001] The invention belongs to the technical field of electrostatic discharge of power semiconductor devices, and in particular relates to a cellular structure and a manufacturing method thereof. Background technique [0002] Electrostatic Discharge (ESD) is an important factor that causes damage to most electronic components. In order to avoid damage to electronic components, electronic engineers have thought of many countermeasures. One of the mainstream ideas is to design ESD for a single device or integrated circuit , that is, by adding ESD protection components to protect the devices or integrated circuits that need to be protected. Widely used ESD protection components include diodes (Diode), bipolar transistors (NPN / PNP), metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon-controlled rectifiers (SCRs), and the like. [0003] Edward John Coyne et al. propose an electrostatic protection component (referring to document 1: Edward JohnC...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L21/77
Inventor 叶俊张邵华
Owner HANGZHOU SILAN MICROELECTRONICS
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