53 results about "Cellular array" patented technology

A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

A semiconductor device according to an embodiment of the present disclosure includes: a memory cell array including a plurality of first selection lines extending in a first direction, a plurality of second selection lines extending in a second direction, and a plurality of memory cells each provided between the plurality of first selection lines and the plurality of second selection lines; a voltage generator that is configured to generate a selection voltage to be applied to one of the plurality of first selection lines; and a decoder section that includes a plurality of selection transistors and a gate driving section, and selects one of the plurality of first selection lines and applies the selection voltage to the selected first selection line, the plurality of selection transistors each provided in a plurality of selection paths coupling the plurality of first selection lines and the voltage generator, the gate driving section that drives gates of the plurality of transistors and is configured to apply a first driving voltage to the gates of the plurality of transistors, the first driving voltage being a positive voltage exceeding a withstand voltage of the plurality of selection transistors.

A battery system includes an array of cells and an insulating plate. The array of cells is arranged in first and second subsets of cells. The first and second subsets of cells define a space therebetween. The insulating plate has a central region disposed within the space. The insulating plate has first and second lateral regions disposed external to the space and extending beyond first and second opposing lateral ends of the array of cells, respectively. The central region has a first dimension extending in a first direction between the first and second subsets of cells. The first and second lateral regions have second and third dimensions, respectively, extending in a second direction. The second direction is substantially parallel to the first direction. The second and third dimensions are greater than the first dimension.

The invention discloses a width-adjustable wide-frequency-domain acoustic waveguide based on an interval coupling type topological boundary state, and belongs to the technical field of topological photonic crystals. The acoustic waveguide comprises interval coupling type topological boundary state scatterers and a substrate, and is characterized in that the interval coupling type topological boundary state scatterers are all arranged on the substrate; the periodically arranged scatterers form a cellular array, the scatterers are divided into I-type photonic crystals PnC1 and II-type photonic crystals PnC2 according to the rotation angles of the scatterers, a plurality of topological paths are constructed by arranging the two photonic crystals in a spaced coupling mode, and the wide-frequency-domain acoustic waveguide with the adjustable width is achieved. The width-adjustable acoustic waveguide is realized by introducing a plurality of topological paths, and low-loss, high-efficiency and wide-frequency-domain unidirectional transmission of acoustic wave signals along the topological paths is finally realized. The waveguide has high robustness and width adjustability, and a new thought is provided for solving the problem of connection between a topological structure and block equipment.

There is provided a method and a system configured to compensate for image distortions. An example method includes first receiving a warped image of an array of cells of a specimen. Each cell of the array comprises one or more structural elements of a substrate. A reference image of a region associated with a cell of the array of cells is generated and a first cell of the array of cells is identified using the reference image and at least part of the warped image. One or more locations comprising cells that differ from the first cell are identified and, based at least on the one or more locations, a warped compensation transform is determined. The warped compensation transform is applied on the warped image to generate an undistorted image.

A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit, and a lower insulating structure on the peripheral circuit, a cell array structure having a cell area and a peripheral connection area and including an upper insulating structure in contact with the lower insulating structure, a cell stack in the cell area on the upper insulating structure, a common source line layer on the cell stack and having a common source opening, a plurality of cell channel structures extending in a vertical direction in the cell stack and into the common source line layer, and a support structure extending in the vertical direction in the cell stack and into the common source opening, and a pad pattern extending from the peripheral connection area to the cell area on the cell array structure and overlapping the support structure in the vertical direction.

This invention discloses a multi-domain joint error correction system for a dual-frequency swarm array, belonging to the field of radar signal processing technology. It obtains correction signals from multiple correction sources through time diversity, with each source transmitting correction signals to the swarm array with a position error exceeding half a wavelength via two carrier frequencies. A simplified SMSSWF method is used to estimate the actual steering vectors of the two carrier frequencies. Based on these steering vectors, the equivalent frequency method is used to calculate the position error, obtaining estimated values ​​for the array element position error parameters. After updating the array element position information using these estimated values, the received signals from the two carrier frequencies are used to estimate the position error, phase error, and communication delay error, respectively, completing the joint error correction for the swarm array with a position error exceeding half a wavelength. The dual-frequency position error estimation based on the equivalent frequency method fully utilizes the large error estimation range of the dual-frequency method while retaining the high accuracy of traditional methods, successfully correcting errors even when the position error exceeds half a wavelength.

A semiconductor memory device including a cell array structure (CS) and a peripheral circuit structure (PS) is provided. The cell array structure includes a first stack structure (ST1), a second stack structure (ST2) on the first stack structure, and a third stack structure (ST3) on the second stack structure, each of the first to third stack structures including a plurality of word lines (EL1, EL2, EL3), vertical channel structures (VS) extending into the first to third stack structures, and a second cell contact plug (CP2a, CP2b) extending into the first to third stack structures and connected to a second contact plug at an end of a second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion (LP1, LP2) having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.

A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Provided is an integrated circuit device including a substrate having a cell array area, a peripheral circuit area surrounding the cell array area, and an interface area between the cell array area and the peripheral circuit area, a plurality of bit lines extending in a first horizontal direction on the cell array area and the interface area and placed parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, insulating capping patterns extending in the first horizontal direction on the bit lines, a plurality of contact plugs vertically connected to the bit lines, respectively, in the interface area, and a plurality of contact pads disposed on the plurality of contact plugs, respectively, wherein the contact plugs are spaced apart from centers of the bit lines in the second horizontal direction at a certain gap in the second horizontal direction.

A device for controllably reflecting electromagnetic (EM) waves is provided. The device includes a metasurface having an array of electromagnetic unit cells. The device further includes a controller for controlling, based on an angle of incidence of the EM waves relative to the metasurface and based on a desired anomalous angle of reflection of the EM waves relative to the metasurface, a reflection phase of each unit cell of a supercell of the metasurface to control an angle of reflection of the EM waves relative to the metasurface to be the desired anomalous angle of reflection. The supercell consists of one or more of the unit cells, and a size (D) of the supercell in a direction of a plane of propagation of the EM waves is at least 2λ, wherein λ is a wavelength of the EM waves.

In a vertical power device with trenched insulated gates, there is an npnp layered structure. The vertical gates turn on the device with a suitable gate bias to conduct a current between a top electrode and a bottom electrode. In an example, implanted n+ source regions are formed in the top surface within a p-well. Between some gates, the overlying dielectric is opened up, by etching, to expose distributed p-type contact regions for the p-well. The dielectric is also opened up to expose areas of the n+ source regions. The top electrode metal directly contacts the exposed p-type contact regions and the n+ source regions to provide distributed emitter-to-base short across the cellular array to improve device performance in the presence of transients. The p-contact regions are isolated from the n+ source regions, prior to the deposition of the metal electrode, due to the p-type contact regions not abutting the n+ source regions.

Systems and methods are provided for a radar and cellular system for telematics and radar detecting in vehicles. In one example, the radar and cellular system includes a circuit board with layers including a top, a bottom, and a separating layer interposed between the top and the bottom, a radar array electrically coupled to the bottom and adapted to transmit and receive radar signals, a cellular array electrically coupled to the top and adapted to transmit and receive cellular signals, a single central processing unit adapted to control the radar signals and the cellular signals in order to perform functions such as occupant detection and diagnostics. The radar and cellular system further includes a single power source adapted to supply power for transmitting the radar signals and the cellular signals.

Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.

Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.

Provided herein systems and methods for processing cryopreserved cells without an expansion phase after thawing, including transfecting cells for gene editing purposes and cryopreserving transfected cells. Systems and methods for high-throughput processing of frozen cells are also provided. The systems and methods provided can be used to modify cells, including gene editing, in cell arrays.

The invention relates to a method for predicting the surface quality of a workpiece milled by a micro-texture ball-end milling cutter under heat-assisted laser, and belongs to the technical field of surface quality prediction. Comprising the following steps: data processing; converting the normalized data into a cellular array format; defining an optimization target; defining a hyper-parameter search space; executing Bayesian optimization to search parameters; constructing a model; training options are set; a training Network function is used to train a model to carry out prediction; carrying out reverse normalization operation on the prediction result; and the network structure of the model is checked by using an anilyzeNetwork function. According to the method, the BO-Transform-LSTM regression analysis model is established to process and predict the surface roughness of the workpiece, the vibration signal obtained after noise reduction processing is stable in noise reduction and good in decomposition accuracy, the training set decision coefficient and the test set decision coefficient obtained through prediction of the BO-Transform-LSTM regression analysis model can accurately predict the surface roughness of the workpiece, and the accuracy of the surface roughness of the workpiece is improved. Therefore, the stability of the cutting process and the machining quality are guaranteed.

The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source / drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source / drain region has a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

A cell stack device includes a cell stack constituted by arraying and electrically connecting cells, and a pair of conductive members respectively located on two ends of the cell stack in an array direction of the cells and electrically connected to the cells. Each conductive member includes a power receiving portion facing the cell stack and a current extraction portion extending from the power receiving portion. The current extraction portion includes an extraction portion body and a connecting portion to be connected to an external device. When a direction in which the current extraction portion extends from the power receiving portion is defined as a first direction and a direction orthogonal to the first direction is defined as a second direction, the extraction portion body includes, in the second direction, a first part shorter in length than an average length of the extraction portion body.

An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

A system and method for sequencing a molecule, where the system includes: a nanopore sensor chip (602) with an array (200) of cells, where each cell of the array of cells has a working electrode (202) and a switch (406). The system also has a flow channel configured to flow an analyte comprising the molecule across the array of cells; a counter electrode (210) configured to apply a voltage to the analyte; an alternating current voltage source (228) configured to apply an AC voltage to the working electrode (202); a storage device (612) configured to represent either an open state or a closed state for the switch (406); an analog-to-digital converter (410); and one or more processors (430). The one or more processors (430) are programmed to: (1) analyze output data from the analog-to-digital converter (410) to detect a first sub-set of cells, where each cell of the first sub-set cells comprises a membrane with a nanopore embedded therein; (2) analyze further output data from the analog-to-digital converter (410) for the first sub-set of cells to detect a second sub-set of cells, where the first sub-set of cells comprises the second sub-set of cells; and in response to this analysis of the further output data: (3) update the state of the storage device (612) of each cell of the second sub-set of cells to an open state, thereby opening the switch (406) of each cell of the second sub-set of cells so as to disconnect the working electrode (202) of each cell of the second sub-set of cells from the AC voltage source (228) for a period of time during a single AC modulation period.

The embodiment of the invention provides a cell assembling method. The cell assembling method comprises the following steps: preparing an assembling pool; the assembling pool is provided with a first inner cavity and a second inner cavity, the first inner cavity is communicated with the second inner cavity through a communicating port, the inner diameter of the second inner cavity is smaller than that of the first inner cavity, and the first inner cavity is connected with the second inner cavity through a connecting surface surrounding the communicating port; placing a porous film on the connecting surface, and enabling the porous film to completely cover the communicating port; the porous film is provided with a micropore array; preparing a cell suspension; the cell suspension contains cells to be assembled; cell suspension is injected into the first inner cavity or the second inner cavity, positive pressure or negative pressure is applied to the first inner cavity or the second inner cavity so that pressure difference can be generated between the first inner cavity and the second inner cavity, and the cells to be assembled in the cell suspension are driven by the pressure difference to enter the micropores of the micropore array and are captured by the micropores. And the cell array assembled on the porous film is obtained. The cell assembling method is good in universality, rapid and efficient in assembling and high in cell coverage rate.

A method of forming a plurality of lipid bilayers over an array of cells in a nanopore based sequencing chip is disclosed. Each of the cells comprises a well. A first salt buffer solution with a first osmolarity is flowed over a cell in the nanopore based sequencing chip to substantially fill a well in the cell with the first salt buffer solution. A lipid and solvent mixture is flowed over the cell to deposit a lipid membrane over the well that encloses the first salt buffer solution in the well. A second salt buffer solution with a second osmolarity is flowed above the well to reduce the thickness of the lipid membrane, wherein the second osmolarity is a lower osmolarity than the first osmolarity such that an osmotic imbalance is created between a first volume inside the well and a second volume outside the well.

The invention discloses a method for culturing an organoid microarray based on surface acoustic wave acoustic tweezers and application, and relates to the field of organoid culture. The invention aims to solve the technical problems of non-uniform size, low flux and poor repeatability in traditional organoid culture. The method comprises the following steps: bonding a microarray cavity at an orthogonal center point position of an interdigital transducer; interdigital electrodes of the interdigital transducers are connected with a signal generator; and injecting the cell culture fluid into the microarray chamber, starting the signal generator, controlling the culture of the organoid microarray through the acoustic surface waves generated by the acoustic surface wave acoustic tweezers, closing the signal generator after the culture is completed, and discharging the cell culture fluid from the liquid outlet of the microarray chamber. The acoustic tweezers equipment has the cell array distribution capacity, and compared with a traditional method, the method has the advantages of being non-contact, harmless to cells and the like. The method is used for culturing the organ-like microarray.

The solid hydrogen storage device comprises a shell and a cavity defined by the shell, the interior of the cavity is divided by partition plates to form a plurality of independent spaces, the cross sections of the independent spaces are arranged in a cellular array mode, one end of each independent space is fixedly connected with the bottom face of the shell, the other end of each independent space is open, and the independent spaces are filled with hydrogen storage material powder. A layer of nickel filter screen is arranged at the opening end of the independent space, an opening hole is formed in the shell close to the nickel filter screen, and an internal thread used for being connected with a valve is arranged on the opening hole. According to the solid hydrogen storage device, structure and function integrated Al-5Ce-2Ni-0.5 Zr alloy powder with high heat conductivity, high toughness and high creep resistance serves as a raw material, the solid hydrogen storage device is integrally formed through the selective laser melting technology, the weight percentage of the hydrogen storage material is increased to 95% or above from 70%-80% of a traditional solid hydrogen storage device, the hydrogen storage amount is increased by 15% or above, the highest pressure bearing capacity reaches 15 MPa, and the hydrogen storage effect is good. The hydrogen storage device has the remarkable advantages and characteristics of safety, high efficiency, high production efficiency and low cost.

A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

The invention discloses a micro-fluidic chip for constructing a high-throughput single cell transcriptome sequencing library and a construction method, and relates to the field of micro-fluidic chips. The micro-fluidic chip comprises a substrate layer, an electrode layer and a capture layer, the capture layer comprises a body and a micro-well structure, and the micro-well structure comprises a first micro-well, a second micro-well and a channel connecting the first micro-well and the second micro-well; the micro-fluidic chip further comprises a magnetic component; wherein the magnetic beads with the biological bar codes are captured by the first micro-trap with a magnetic part at the bottom, and cells to be subjected to transcriptome sequencing are captured by the second micro-trap by utilizing a dielectrophoresis technology. Magnetic beads with bio-barcodes and cells to be subjected to transcriptome sequencing are captured in an active capture mode and are respectively captured into a first micro-trap and a second micro-trap, a high-throughput single magnetic bead-single cell array is formed, the single cell capture rate and the test flux of a single sample are improved, mRNA is released in an electro-rupture membrane mode, and the test efficiency is improved. MRNA can be quickly released, and cross contamination is avoided.