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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of reduced electrostatic discharge protection ability and high cost

Pending Publication Date: 2021-07-30
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the prior art, in order to overcome the problem of the decrease of electrostatic discharge protection ability brought about by the lightly doped drain (Lightly Doped Drain, LDD) structure, the electrostatic discharge ion implantation (ESD implant) technology is usually combined with the silicide baffle (Salicide Blocking (SAB) process, using SAB technology to increase the resistance of the drain region to improve the current discharge capability of the device, so that the current can flow uniformly in the silicon wafer, and the ESD device needs a SAB mask to improve the ESD protection capability of the device , while the cost of the SAB mask is relatively high, and reducing the mask can reduce the manufacturing cost, especially for the design and manufacture of nanoscale integrated circuits

Method used

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  • Semiconductor device
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Embodiment 1

[0027] figure 1 This is a schematic structural diagram of the semiconductor device provided in this embodiment. This embodiment provides a semiconductor device to improve the ESD capability of the device and reduce the manufacturing cost of the device. Please refer to figure 1 , the semiconductor device includes a substrate 10 , three sub-drain regions 21 , two dummy structures 22 , a source region 31 and a gate structure 40 .

[0028] The substrate 10 has a first area 20 and a second area 30 , and the first area 20 is located between two adjacent second areas 30 . The substrate 10 has the second conductivity type, and the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon. Both the first well region 11 and the second well region 12 are located in the substrate 10 , the first well region 11 is located between two adjacent second well regions 12 , wherein the first well region 11 In the first region 20 of the substrate 10 , ...

Embodiment 2

[0036] figure 2 This is a partial structural schematic diagram of the semiconductor device provided in this embodiment. Please refer to figure 2 , figure 2 Provided for Example 1 figure 1 Schematic diagram of the structure at the first area, the difference between this embodiment and Embodiment 1 is that the structure of the dummy structure 22' is different. In this embodiment, the dummy structure 22' is a FLASH structure. The structure will not be described in detail, and those skilled in the art can configure it according to the actual situation. In this embodiment, neither the SAB mask of the prior art nor the introduction of a new process flow is required. The dummy structure 22' is simultaneously fabricated in the FLASH structure preparation process, and no redundant mask is required, and no new process is required. Process flow, reducing the mask can save the manufacturing cost of the device.

[0037] In this embodiment, it is not necessary to form a shallow tren...

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Abstract

The invention provides a semiconductor device comprising a substrate having a first region and second regions, the first region being located between two adjacent second regions; three sub drain regions located in the first region of the substrate; two dummy structures respectively positioned on the substrate between the two adjacent sub drain regions; a source region located in the second regions of the substrate; a gate structure positioned on the substrate between the first region and the second regions. The ESD capacity of the device is improved through the dummy structure, an SAB photomask in the prior art is not needed, a new technological process does not need to be introduced, and the dummy structure can be directly and synchronously formed in the manufacturing process, so that the manufacturing cost of the device is reduced.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device. Background technique [0002] As semiconductor device technology continues to move into sub-micron and deep sub-micron, ESD protection device reliability becomes more and more important. Due to electrostatic discharge (Electro-Static-Discharge, ESD), the discharge current flows in the device and generates local heating or electric field concentration, which is prone to electrostatic damage in the device, resulting in failure of the IC device; a short circuit to the ground at one terminal of the device , then a current pulse is generated at the moment of discharge, and the Joule heat generated by the large current causes local metallization of the device to melt or hot spots on the chip to induce secondary breakdown, etc.; when the device is not in contact with the ground, there is no direct discharge path to the ground, and It is to tr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0292
Inventor 严强生刘冲陈宏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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