4685results about How to "Reduce yield" patented technology

A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Described herein are methods for the efficient production of antibodies and other multimeric protein complexes (collectively referred to herein as heteromultimeric proteins) capable of specifically binding to more than one target. The targets may be, for example, different epitopes on a single molecule or located on different molecules. The methods combine efficient, high gene expression level, appropriate assembly, and ease of purification for the heteromultimeric proteins. The invention also provides methods of using these heteromultimeric proteins, and compositions, kits and articles of manufacture comprising these antibodies.

The invention provides a high throughput, high purity, high yield system and method of isolating and purifying rebaudioside A (“Reb A”), with acceptable water solubility for all commercial uses, from commercially available Stevia rebaudiana starting material. The invention also provides a means of maximizing yields of 99+% purity Reb A based on the attributes of a given batch of Stevia starting material. The Reb A produced by the invention is water soluble, devoid of bitterness heretofore associated with rebaudioside sweeteners, non-caloric, and suitable for use as a reagent and as an ingredient in orally consumed products, e.g., as a sweetener, flavor enhancer, and flavor modifier.

To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.

An organic electroluminescent device including: an anode, a cathode, and at least an emitting layer, an electron-transporting layer and an electron-injecting layer interposed between the anode and the cathode; the emitting layer containing a host material which is a pyrene derivative, a chrysene derivative, a fluorene derivative or an anthracene derivative; the electron-transporting layer containing an electron-transporting material which is a pyrene derivative, a chrysene derivative, a fluorene derivative or an anthracene derivative, the anthracene derivative containing no heterocyclic ring, and has a heterocyclic ring and having a fluorescence quantum yield which is smaller than that of the host material contained in the emitting layer; and the electron-injecting layer containing a non-complex compound having a nitrogen-containing five-membered heterocyclic structure.

It includes the stages of grinding the lignocellulosic biomass to a size of 15-30 mm, subjecting the product obtained to steam explosion pre-treatment at a temperature of 190-230° C. for between 1 and 10 minutes in a reactor (2), collecting the pre-treated material in a cyclone (3) and separating the liquid and solid fractions by filtration in a filter press (9), introducing the solid fraction in a fermentation deposit (10), adding a cellulase at a concentration of 15 UFP per gram of cellulose and 12.6 International Units of β-glucosidase enzyme dissolved in citrate buffer pH 4.8, inoculating the fermentation deposit (10) with a culture of the heat-tolerant bacteria Kluyveromyces marxianus CECT 10875, obtained by chemical mutagenesis from strain DER-26 of Kluyveromyces marxianus and shaking the mixture for 72 hours at 42° C.

A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the metallic oxide, in which the channel region exhibits semiconductor characteristics and the oxygen content decreases with depth below the surface.

To improve viewing angle characteristics by varying voltage which is applied between liquid crystal elements. A liquid crystal display device in which one pixel is provided with three or more liquid crystal elements and the level of voltage which is applied is varied between the liquid crystal elements is varied. In order to vary the level of the voltage which is applied between the liquid crystal elements, an element which divides the applied voltage is provided. In order to vary the level of the applied voltage, a capacitor, a resistor, a transistor, or the like is used. Viewing angle characteristics can be improved by varying the level of the voltage which is applied between the liquid crystal elements.

A circularly polarizing plate comprises a linearly polarizing membrane and a quarter wave plate. The quarter wave plate comprises an optically anisotropic layer A and an optically anisotropic layer B. The quarter wave plate has such an optical characteristic that a retardation value essentially is a quarter of a wavelength when the retardation value is measured at the wavelength of 450 nm, 550 nm and 650 nm. One of the optically anisotropic layers A and B is a layer made from liquid crystal molecules, and the other is a polymer film or a layer made from liquid crystal molecules.

A process for manufacturing a lubricating base oil by: a) performing Fischer-Tropsch synthesis on syngas to provide a product stream; b) isolating from said product stream a substantially paraffinic wax feed having less than about 30 ppm total nitrogen and sulfur, and less than about 1 wt % oxygen; c) dewaxing said feed by hydroisomerization dewaxing using a shape selective intermediate pore size molecular sieve comprising a noble metal hydrogenation component, wherein the hydroisomerization temperature is between about 600° F. (315° C.) and about 750° F. (399° C.), to produce an is dimerized oil; and d) hydrofinishing said isomerized oil to produce a lubricating base oil having specific desired properties.

A method and apparatus for inspecting the surface of articles, such as chips and wafers, for defects, includes a first phase of optically examining the complete surface of the article inspected at a relatively high speed and with a relatively low spatial resolution, and a second phase of optically examining with a relatively high spatial resolution only the suspected locations for the presence or absence of a defect therein.

The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

A method for manufacturing reflective spatial light modulator mirror devices is disclosed. In the method, a portion of a mirror layer and a first sacrificial layer beneath the portion of the mirror layer are removed simultaneously to expose the substrate while defining a pattern of the mirror layer. Then, a second sacrificial layer is deposited conformally, and substrate contact openings and a mirror layer contact opening are defined in the second sacrificial layer at the same time. Subsequently, a support material layer is deposited conformally and etched back, so as to form supporting posts of the mirror layer in the substrate contact openings. Before the support material layer is etched back, the substrate contact openings can be filled with a photoresist material first, so as to maintain the support material layer in the substrate contact openings and increase the structural intensity of the supporting posts.

Methods and systems for evaluating and controlling a lithography process are provided. For example, a method for reducing within wafer variation of a critical metric of a lithography process may include measuring at least one property of a resist disposed upon a wafer during the lithography process. A critical metric of a lithography process may include, but may not be limited to, a critical dimension of a feature formed during the lithography process. The method may also include altering at least one parameter of a process module configured to perform a step of the lithography process to reduce within wafer variation of the critical metric. The parameter of the process module may be altered in response to at least the one measured property of the resist.

An object is to propose a method of manufacturing, with high mass productivity, liquid crystal display devices having thin film transistors with highly reliable electric characteristics. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

An object is to provide a technology capable of improving a manufacturing yield of semiconductor devices by preventing scattering of irregular-shaped scraps formed at the time of dicing. To achieve the above object, for dicing lines, by which an irregular-shaped outer periphery may possibly be cut off, among a plurality of dicing lines, formation of the dicing lines starts from an outside of a semiconductor wafer, and after the semiconductor wafer is cut off partway, formation of the dicing lines is ended before reaching the irregular-shaped outer periphery formed on a outer periphery of the semiconductor wafer. For other dicing lines, formation of the dicing lines starts from the outside of the semiconductor wafer, and after the semiconductor wafer is cut off, is ended outside the semiconductor wafer.

For the high spatial resolution imaging of a structure of interest in a specimen, a substance is selected from a group of substances which have a fluorescent first state and a nonfluorescent second state; which can be converted fractionally from their first state into their second state by light which excites them into fluorescence, and which return from their second state into their first state; the specimen's structure of interest is imaged onto a sensor array, a spatial resolution limit of the imaging being greater (i.e. worse) than an average spacing between closest neighboring molecules of the substance in the specimen; the specimen is exposed to light in a region which has dimensions larger than the spatial resolution limit, fractions of the substance alternately being excited by the light to emit fluorescent light and converted into their second state, and at least 10% of the molecules of the substance that are respectively in the first state lying at a distance from their closest neighboring molecules in the first state which is greater than the spatial resolution limit; and the fluorescent light, which is spontaneously emitted by the substance from the region, is registered in a plurality of images recorded by the sensor array during continued exposure of the specimen to the light.

The invention provides a polishing pad by which optical materials such as lenses, reflecting mirrors etc., or materials requiring a high degree of surface planarity, as in the polishing of silicone wafers, glass substrates or aluminum substrates for hard disks, or general metal polishing, can be flattened with stability and high polishing efficiency. The invention also provides a polishing pad for semiconductor wafers, which is superior in planarizing characteristic, is free from scratches and can be produced at low cost. There is provided a polishing pad which is free from dechucking error so that neither damage to wafers nor decrease in operating efficiency occurs. There is provided a polishing pad which is satisfactory in planarity, within wafer uniformity, and polishing rate and produces less change in polishing rate. There is provided a polishing pad which can make planarity improvement and scratch decrease compatible.

A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade.

An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

The lighting system according to the present invention includes an electrical wiring substrate in which a connector to a power source is formed, a plurality of LED chips mounted in a predetermined array pattern on the electrical wiring substrate, a deflection lens array disposed in proximity to the LED chips between the LED chip and the predetermined illumination region and a housing for receiving the electrical wiring substrate and the deflection lens array. A plurality of deflection lenses are integrally molded in the deflection lens array to lead lights from the LED chips to the predetermined illumination region in a state where the lights from the LED chips are superposed with each other. The lights emitted from the LED chips are collected in a state where they all are superposed in a common, single illumination region through the deflection lenses.

The invention provides a method of managing fertiliser and irrigation inputs for a crop, the method comprising obtaining management data for the crop, the management data including a planting date for the crop; obtaining weather data representative of the geographic area of the crop; obtaining soil description data representative of the geographic area of the crop; calculating an emergence date at least partly from the planting date; calculating a plurality of nitrogen deficit values at least partly from the emergence date and the soil description data, the nitrogen deficit values associated with respective dates each later than the emergence date; calculating a plurality of water deficit values at least partly from the emergence date and the weather data, the water deficit values associated with respective dates each later than the emergence date; and presenting on a display a schedule of recommended nitrogen application values, irrigation values and application dates, the schedule calculated at least partly from the nitrogen deficit values and the water deficit values.