Trigger circuit structure with integrated circuit power supply rail antistatic protection

Abstract

The invention provides a trigger circuit structure with circuit power supply rail antistatic protection, belonging to the technical field of electronics. The structure is used for triggering an integrated circuit high voltage power supply rail antistatic protective device with mixed working voltage, and comprises a series circuit, a second PMOS (positive channel metal oxide semiconductor) tube and a resistor R, wherein the series circuit consists of m (a positive integer) first PMOS tubes and is formed by connection of diodes; the source electrode of the most top first PMOS tube in the series circuit is connected with VDD_H (voltage drain drain_high); the drain electrode of the second PMOS tube is connected with a triggering end T of an ESD (electro-static discharge) protective device; the grid electrode of the second PMOS tube is connected with VDD (voltage drain drain) through the resistor R. The trigger circuit structure consists of a low voltage device, however, the trigger circuit structure can tolerate VDD_H voltage of a high voltage power supply rail, reduce the trigger voltage of the device, promote uniform conduction of the device, and improve ESD capability, and meanwhile, no capacitor device exists in the circuit, thus, the leakage current of the protected integrated circuit under normal working is smaller.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to the design of an electrostatic discharge (ESD for short) protection circuit for a semiconductor integrated circuit chip, in particular to a power rail for two (or more) different voltages, and is only controlled by Electrostatic protection design technology for integrated circuits composed of low-voltage devices. Background technique [0002] With the continuous development of CMOS technology, the number of transistors integrated on each chip has also increased dramatically. However, in a complex system, when different chips are connected to each other, since the working voltage of the chip may be different, its I / O interface circuit may need to receive or output signals of different voltage values. This requires the I / O interface circuits between chips to be able to withstand different voltages. However, for integrated circuits operating at low voltage, the gate oxide layer ...

AI Technical Summary

Problems solved by technology

However, under the advanced CMOS process, the area of ​​the capacitor is much larger than the area of ​​the transistor, and due to the influence of its parasitic resistance, the capacitor cannot completely block the current, and the ESD protection device will be weakly turned on, which will cause a large Leakage current, resulting in higher power consumption when the chip is working

Images