Full-chip electrostatic discharge network

An electrostatic discharge, full-chip technology, applied in circuits, electrical components, electric solid devices, etc., can solve problems such as not helping to discharge electrostatic charges, affecting the anti-static ability of devices, etc.

Inactive Publication Date: 2019-01-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this time, the drive tubes of other IO units are in an uncertain state, which cannot help

Method used

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  • Full-chip electrostatic discharge network
  • Full-chip electrostatic discharge network

Examples

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Embodiment Construction

[0020] The full-chip electrostatic discharge network of the present invention, such as figure 2 As shown, it includes a power clamp circuit (PowerClamp) and multiple identical IO units connected in parallel.

[0021] The power supply clamping circuit is connected between the power supply and the ground, and the power supply clamping circuit also includes an ESD detection circuit for detecting ESD signals, and will generate a trigger signal after detecting the ESD signals; It also includes an electrostatic discharge transistor, and the detected ESD signal is simultaneously provided to the gate of the electrostatic discharge transistor. This transistor is used to release the static electricity on the power supply to the ground line, and this transistor is an NMOS transistor (BigNMOS) whose size is much larger than other transistors.

[0022] The multiple IO units include n identical units from IO(1) to IO(n), which are connected in parallel and then connected in parallel with ...

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PUM

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Abstract

The invention discloses a full-chip electrostatic discharge network, which comprises a power clamp circuit and a plurality of IO units. The power clamp circuit is connected between the power supply and the ground. The power clamp circuit also comprises an ESD detection circuit, which is used for detecting the ESD signal and generating a trigger signal after detecting the ESD signal. The pluralityof IO units are a plurality of IO units connected in parallel and connected between the power supply and the ground as well as the power clamp circuit. Each unit of the IO units has an IO port, and the IO port is an IO port which will be affected by the electrostatic discharge. The IO unit comprises a precursor circuit, a control circuit and a back drive circuit, wherein the control circuit and the back drive circuit are connected with a power supply and a ground; All the precursor circuits of the IO unit are connected to the ESD trigger signal terminal of the ESD detection circuit to receivethe ESD trigger signal, and then the output terminal of the precursor circuit generates a corresponding control signal to be provided to the control circuit.

Description

technical field [0001] The invention relates to the field of design and manufacture of semiconductor devices, in particular to a full-chip electrostatic discharge network. Background technique [0002] Static electricity is an objective natural phenomenon, which can be produced in many ways, such as contact, friction, induction between electrical appliances, etc. Static electricity is characterized by long-term accumulation, high voltage, low power, small current and short action time. Static electricity causes serious harm in many fields. Friction electrification and human body static electricity are two major hazards in the electronics industry, which often cause unstable operation or even damage of electronic and electrical products. [0003] As the feature size of the semiconductor integrated circuit manufacturing process becomes smaller and smaller, the size of the chip unit is also smaller and smaller, and the antistatic ability of the chip becomes more and more impo...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0248
Inventor 吕斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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