Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM

A technology for writing circuits and reading circuits, which is applied in information storage, static memory, digital memory information, etc., and can solve problems such as complex structure, inability to control the threshold value by the user later, and different opening properties of the threshold voltage

Inactive Publication Date: 2013-10-09
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70% of the silicon Chip area; in programmable logic devices (such as FPGA and CPLD), there are also a large number of programmable internal wiring (including programmable connection switches, such as fuse switches, anti-fuse switches, floating gate programming components, etc.), Connect each logic function block or input/output to complete a specific function circuit, wiring (including programming connection switch) accounts for a large cost of materials
[0006] 2. In the realization of multi-valued circuits, the existing technology to control the threshold of MOS transistors has great disadvantages: ① the amplitude of the control threshold is limited (because the ion implantation concentration is limited), and the resolution of opening is low; and the amplitude of the control threshold in the process is often Change the performance of the MOS tube, for example, the decrease of the threshold voltage will lead to a sharp increase of the cut-off current, the adjustment of the threshold voltage will affect the perfor

Method used

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  • Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM
  • Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM
  • Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM

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Experimental program
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Effect test

Embodiment 1

[0044] Embodiment 1: Description of the circuit information function of the storage unit.

[0045] The storage unit circuit has three information functions of multi-value information storage, multi-value information reception and multi-value information sending: ①Information reception: by figure 1 It can be seen that the write pulse w ri When coming, the transfer gate G 1 conduction, will write the bit line G wrij The multi-valued information is transferred to the storage capacitor C j , so that the capacitor C j Receive multi-valued information C mij ; Capacitance C j Reception is a charging and discharging process, whether charging or discharging depends on the capacitance C j The original stored information and the current received information, the charging and discharging time constant is C j Capacitance related, C j Usually only a few picofarads, no larger; ②Information storage: write pulse w ri When the future arrives, the transmission gate G 1 due by figure...

Embodiment 2

[0049] Embodiment 2: Proof that the writing circuit of arbitrary K value and 8-value DRAM satisfies design requirements.

[0050] The writing circuit of any K value DRAM is shown as Figure 4 , it is necessary to prove that the design requirements are met: when writing into the circuit input D inj When the logic value is 0, 1, 2, 3, 4, ..., L-2, L-1, L, write circuit output G wrij Logical values ​​are still sequentially 0, 1, 2, 3, 4, ..., L-2, L-1, L; but G wrij Logical value corresponds to logic level V Gwrij (n) than D except 0 level inj Logical value corresponds to logic level V Dinj (n) High Δ (n=1~L), the 0 level is still 0, that is, V Gwrij (0)=V Dinj (0) = 0V, V Gwrij (1) = V Dinj (1)+Δ, V Gwrij (2) = V Dinj (2)+Δ,...,V Gwrij (L-1)=V Dinj (L-1)+Δ, V Gwrij (L)=V Dinj (L)+Δ, V Dinj (k)>V Dinj (k-1); ta k Adjacent logic level V for the write circuit input Dinj (k) and V Dinj The middle value of (k-1), satisfying V Dinj (k-1)k Dinj (k), k=1, 2, 3, 4, ......

Embodiment 3

[0053] Embodiment 3: Proof that the readout circuit of any K value and 8-value DRAM satisfies the design requirements.

[0054] The readout circuit of any K value DRAM is shown as Figure 5 , it is necessary to prove that the design requirements are satisfied: when the input G of the readout circuit rdij When the logic value is 0, 1, 2, 3, 4, ..., L-2, L-1, L, the input D of the readout circuit outj Logical values ​​are still sequentially 0, 1, 2, 3, 4, ..., L-2, L-1, L; G rdij ,D inj and D outj The logic value corresponds to the logic level in order of V Grdij (n), V Dinj (n) and V Doutj (n)(n=0~L), where input G rdij It is a non-standard K value signal, and it is required to output D outj is the standard equal-step K value signal, that is, V Doutj (0)=V Dinj (0) = 0V, V Doutj (1) = V Dinj (1) = V Don , V Doutj (2) = V Dinj (2) = 2V Don , V Doutj (3) = V Dinj (3) = 3V Don ,...V Doutj (L-2)=V Dinj (L-2)=(L-2)V Don , V Doutj (L-1)=V Dinj (L-1)=(L-1)V Do...

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Abstract

The invention relates to write-in circuits and read-out circuits of an arbitrary-K-value DRAM and an eight-value DRAM. The write-in circuits and the read-out circuits have same structure characteristics, and the write-in circuits are each designed to provide a multi-value signal increased by delta than write-in circuit input; an output waveform of a memory cell is considered to be smaller than an input waveform or be of an unequal step shape, the read-out circuits are each designed for correction, and an irregular multi-value signal is converted into a regular (equal step) multi-value signal. The write-in circuits and the read-out circuits both have good quantified shaping effects; when a change of a Cj voltage is not greater than an upper new threshold or a lower new threshold, original multi-value information can be easily recovered, so the write-in circuits and the read-out circuits have anti-jamming capability and multi-value information recovery capability. The write-in circuits and the read-out circuits are mainly applied to the fields of VLSI and other digital IC technologies, such as an FPGA, a CPLD, a semi-custom or a full-custom ASIC, a memorizer and the like.

Description

technical field [0001] The present invention is directed to a divisional application with application number: 201110097206.7, and belongs to the field of digital integrated circuits, specifically a writing circuit and a reading circuit of an arbitrary K value and 8-value DRAM. Background technique [0002] With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70% of the silicon Chip area; in programmable logic devices (such as FPGA and CPLD), there are also a large number of programmable internal wiring (including programmable connection switches, such as fuse switches, anti-fuse switches, floating gate programming components, etc.), To connect each logic function block or input / output to complete a specific function circuit, wiring (including programming connection switches) accounts for a...

Claims

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Application Information

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IPC IPC(8): G11C11/4096
Inventor 方振贤刘莹
Owner HEILONGJIANG UNIV
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