A Parallel Pseudo-CSD Encoder for Variable Coefficient Multipliers

Abstract

The invention relates to the technical field of integrated circuits, in particular to a parallel pseudo-CSD encoder used for variable coefficient multipliers. The parallel pseudo-CSD encoder of the present invention comprises an operation logic circuit and an output logic circuit; the input terminal of the operation logic circuit is connected with external input data, and its output terminal is connected with the first input end of the operation logic circuit; the output terminal of the output logic circuit The second input terminal is connected to external input data, and its output terminal is connected to the coefficient input terminal of the subsequent multiplier. The beneficial effect of the present invention is that while ensuring that the code system after the pseudo-CSD encoding has the same number of non-zero bits as the traditional CSD encoding, parallel operation logic is used to eliminate the carry propagation logic generated in the traditional CSD encoding process, thereby improving the pseudo-CSD The operation speed of the encoder makes it irrelevant to the length of binary digits to be encoded, and belongs to a fixed-delay encoding circuit, which greatly improves the data throughput capability of the pseudo-CSD encoder. The invention is especially applicable to parallel pseudo-CSD encoders with variable coefficient multipliers.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a parallel pseudo-CSD encoder used for variable coefficient multipliers. Background technique [0002] Variable coefficient multiplier is a very important basic unit in digital integrated circuits. In digital system design, the parameters of the multiplier largely affect the parameter performance of the entire digital system. In binary multiplication, each non-zero bit of the coefficient generates a partial product, and then all the partial products are accumulated by an adder to obtain the final result. Generally speaking, the multiplier will use the encoder to encode the coefficients, thereby reducing the number of non-zero bits in the coefficients to reduce the generation of partial products, thereby reducing the number of adders, reducing power consumption and area, and improving the performance of the multiplier. purpose of speed. Among them, the CSD (Canonica...

AI Technical Summary

Problems solved by technology

Due to the influence of carry propagation, the delay time of the traditional CSD encoder, the encoding speed is proportional to the bit length N of the binary number, so that the data throughput of the CSD encoder is limited by the number of encoding bits, which in turn restricts the working speed and data of the multiplier. throughput capacity

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