38 results about "Sign extension" patented technology

A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and / or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and / or arithmetically combining the outputs of multiple multipliers.

A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero extend or sign extend the remaining most significant bits of the destination data. In an alternative embodiment, the execution unit includes plural multiplexers, one for each section of the destination data. Each multiplexer received data from each section of the source data register or registers. Special codes in the sections of the second source data register may select 0 fill, 1 fill or sign extension from the next most significant section for each multiplexer.

A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

An apparatus and a system, as well as a method and article, may operate to select a group of contiguous communications channels having a specified number of channels, a center channel, and a control channel. Some embodiments may operate to select a group of contiguous communications channels having a specified control channel and a signed extension channel offset.

An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

The disclosed optimization method separates data signal from pilot signal, which pass through sign extension portion and IFFT portion respectively. The data portion passes through clipping module then. Optimizing process module carries out optimizing process for data signal. The purpose of the optimizing process is to eliminate influence on the pilot signal by the clipping operation. FFT is carried out for data after self-adapting amplitude limiting in advance so as to convert signal in time domain into signal in frequency domain. Afterwards, the signal in frequency domain passes through module for limiting and eliminating amplitude of noise. Finally, the method superposes the portion of optimizing processed data signal with the portion of pilot signal, and outputs the superposed signal. Through iterative algorithm, the invention reduces influence on the pilot signal caused by amplitude-limited noise, raises precision for estimating channel so as to raise transmission performance.

A Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard is described with exception handling. Operations including exception handling in a way that does not interfere with execution of data flow operations, overflow detection, zero detection and sign extension are adopted for 2's complement and Carry-Save format.

The invention discloses a mask-based mixed floating point multiplication low power consumption control method. Including the hardware to automatically determine the mixed floating-point multiplication operation type, and fill the high bits of the standard floating-point multiplier and the multiplicand mantissa with all 0s, so that the floating-point multiplier and the multiplicand can be combined with the multiplexed fixed-point hardware multiplier The input bit width is the same; for the floating-point multiplication operation, the filled floating-point multiplier and the multiplicand are obtained according to the preset multiplication coding rules and sign extension rules to obtain partial products, and the invalid mantissa is moved to the high bit, and the mask control is used The invalid mantissa does not participate in the partial product compression sum operation to save logic power consumption. The invention also discloses a mask-based mixed floating-point multiplication low-power control device. The invention supports the multiplexing of fixed-point multiplication hardware to realize the low power consumption control of floating-point multiplication, the hardware automatically detects floating-point multiplication operations, and controls the high-order expansion bit coding based on the mask, which has the advantages of low hardware overhead, easy logic implementation, and simple power consumption control. .