7 results about "Sign extension" patented technology

The invention discloses a high-speed fixed-point multiplication circuit. The multiplication circuit is mainly composed of a multiplier coding module, a partial product generation module, a partial product compression module and a traveling wave carry adder module. The multiplier coding module is composed of a radix-4-Booth coding algorithm and an opposite number generation module, and is used for carrying out three-bit block coding on input multiplication data and generating an opposite number of a multiplicand in advance. The partial product generation module generates a plurality of groups of partial products with symbol extension according to the multiplicand coded signal. And the partial product compression module adopts an improved Wallace compression structure to perform layered compression on the partial product. And the traveling wave carry adder module sums the two groups of results output by compression and outputs a multiplication result. According to the invention, multiplication accumulation series can be reduced, the switching times of invalid signals in the circuit can be reduced, and the longest delay path in an operation link can be shortened, so that fixed-point multiplication which is high in speed, low in power consumption and more favorable for a comprehensive tool in structure is realized.

The embodiment of the invention provides an instruction processing method and device, electronic equipment and a readable storage medium. Under the condition that a compiling environment is a simulator environment, if the actual data bit width of an operand corresponding to a to-be-checked instruction is not matched with the general data bit width corresponding to a target architecture, the to-be-checked instruction is not matched with the general data bit width corresponding to the target architecture; if yes, mapping the operand corresponding to the to-be-checked instruction to a first macro assembly function which corresponds to the to-be-checked instruction and is matched with the actual data bit width of the operand corresponding to the to-be-checked instruction, and generating a target pseudo instruction; the target pseudo instruction is used for performing symbol expansion check on an operand corresponding to the to-be-checked instruction; and under the condition that the instruction execution result of the target pseudo instruction is a first result representing that symbol expansion is incorrect, positioning and symbol expansion optimization are performed on the instruction to be checked. Errors introduced by symbol extension are positioned and solved under the condition that the compiling environment is a simulator environment, it is ensured that all potential risks are eliminated in the simulation debugging compiling stage, errors in actual operation are avoided, and the development efficiency is improved.

A neural processing element is configured with a hardware AND gate configured to perform a logical AND operation between a sign extension signal and a most significant bit ("MSB") of an operand. A state of the sign extension signal can be based on a type of layer of a deep neural network ("DNN") that generated the operand. If the sign extension signal is a logical false, no signal extension is performed. If the sign extension signal is a logical true, a coupler couples an output of the hardware AND gate and the operand, thereby extending the operand from an N-bit unsigned binary value to an N+1-bit signed binary value. The neural processing element can also include another hardware AND gate and another coupler for similarly processing another operand. An output of the couplers for both operands is provided to a hardware binary multiplier.

This application provides apparatus and methods for multiplying, summing, and accumulating multiple groups of compressed bytes. An apparatus and method for performing multiplication, addition, inversion, sign extension, and accumulation of compressed bytes. For example, one embodiment of the processor includes: a decoder for decoding an instruction to generate a decoded instruction including an opcode and a plurality of operands identifying a plurality of compressed data source registers and a compressed data destination register; a first source register for storing a first plurality of compressed signed bytes; a second source register for storing a second plurality of compressed signed bytes; and execution circuitry for executing the decoded instruction, the execution circuitry including: a multiplier circuitry for multiplying each compressed signed byte from the first source register with a corresponding compressed signed byte from the second source register to generate a plurality of temporary products; an adder circuitry for adding the plurality of temporary products to generate a plurality of temporary sums; an inverting and expanding circuitry for inverting each temporary sum in the temporary sums and expanding each temporary sum to a double-word sum; and an accumulator circuitry for adding each double-word sum in the double-word sums to a double word from a third source register to generate a final double-word result; and a compressed data destination register for storing the final double-word result in a specified data element location.

Apparatuses and methods for performing double signed and unsigned multiplication of packed data elements are disclosed. Apparatuses and methods for performing double simultaneous multiplication of packed data elements. For example, one embodiment of a processor includes a decoder to decode a first instruction to generate a decoded instruction, a first source register to store a first plurality of packed byte data elements, a second source register to store a second plurality of packed byte data elements, an execution circuit to execute the decoded instruction, the execution circuit including a multiplier circuit to simultaneously multiply each of the first plurality of packed byte data elements with a corresponding packed byte data element of the second plurality of packed byte data elements to generate a plurality of products, an adder circuit to add a specified set of the products to generate a temporary result for each set of products, a zero or sign extension circuit to zero or sign extend the temporary result for each set to generate an extended temporary result for each set, an accumulation circuit to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results, and a destination register to store the plurality of final results as a plurality of packed data elements in a specified data element location.

A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

The embodiment of the invention provides an instruction optimization method and device, electronic equipment and a readable medium, and relates to the technical field of computers, in the method, a symbol extension instruction in a to-be-optimized code serves as a to-be-optimized instruction. Acquiring a data dependency chain corresponding to a function to which the to-be-optimized instruction belongs as a target dependency chain; the data dependency chain is used for defining data dependency instructions of all variables in the function. And searching a source instruction corresponding to the source operand of the to-be-optimized instruction from the target dependency chain, and taking the source instruction as a source instruction of the to-be-optimized instruction. Under the condition that all the source instructions of the to-be-optimized instruction have symbol extension behaviors, determining the pre-extension data bits corresponding to all the source instructions, and determining the pre-extension data bits corresponding to the to-be-optimized instruction. And on the basis of the pre-extension data bits corresponding to the source instructions and the pre-extension data bits corresponding to the to-be-optimized instruction, the to-be-optimized instruction is simplified, and the generated symbol extension instruction is optimized.