Symbol extension method and structure of multipliers

Abstract

This invention discloses a sign extension method and a structure of a multiplier, which designs multiple complement bits in the codes of sign extension during the code operation used in a multiplier of a DSP without increasing critical paths to reach the aim of reducing the waste to the chip area and reducing the size of the multiplier.

Description

technical field [0001] The invention relates to a sign extension method and structure of a multiplier. By setting a plurality of compensations in the code of the multiplier, the purpose of reducing wasted chip area and making the multiplier smaller is achieved. Background technique [0002] The multiplier (multiplier) is a basic operand component, and the multiplier is almost always used in a large number of complex operations. The most typical operation in the digital signal processor (Digital Signal Processor, DSP) - multiplier accumulator (Multiplier Accumulator, MAC ) also need to use a multiplier, which is widely used in digital signal processing, such as digital filters is the most typical example, in addition, most of the microprocessors today are also equipped with more than one multiply-accumulator MAC, so that the microprocessor The device can complete a multiplication and an addition operation within one instruction time. [0003] Generally speaking, a modified B...

AI Technical Summary

Problems solved by technology

This method can indeed reduce the waste of chip area in actual application, but there is an additional layer of correction columns, which means that the critical path will increase, which will affect performance.

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