14 results about "Multiplier accumulator" patented technology

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

The present application belongs to the field of information technology, and particularly relates to a residual error calibration method and system for an optical multiplier. The present application provides a residual error calibration method and system for an optical multiplier, and the present application is used for error compensation of the optical multiplier, can reduce the equivalent matrix deviation of the optical multiplier caused by non-ideal factors such as process error, limited configuration voltage precision, and realizes the effect of improving the calculation precision of the optical multiplier and the accuracy of applications such as picture pattern recognition. The present application has the beneficial effects that: (1) a compensation method and system for the optical multiplier are provided, and the effect of improving the matrix multiplication calculation precision and the accuracy of applications such as pattern recognition can be realized; (2) the compensation effect can be controlled by setting an arbitrary compensation number.

A method and apparatus for deep learning are disclosed. The apparatus for deep learning includes a processor configured to support a plurality of different operation modes, the processor including a systolic array having a plurality of multiplier accumulator (MAC) units, and a control circuit configured to control a selection operation of the plurality of MAC units and a data movement between the plurality of MAC units, respectively, for each of the plurality of different operation modes.

An integrated circuit includes a memory for storing image data and filter weights, and a plurality of multiplier-accumulator execution pipelines, each of the multiplier-accumulator execution pipelines being coupled to the memory to receive (i) image data and (ii) filter weights, wherein each multiplier-accumulator execution pipeline processes the image data using associated filter weights via a plurality of multiplication and accumulation operations. In one embodiment, the multiplier-accumulator circuitry of each multiplier-accumulator execution pipeline receives a different set of image data, each set including a plurality of image data, and processes the associated image data set using the filter weights associated with the received image data set, performing a plurality of multiplication and accumulation operations in parallel with the multiplier-accumulator circuitry of the other multiplier-accumulator execution pipelines, thereby generating output data. Each image data set includes all of the images associated with the output data generated therefrom.

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values, and a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. The X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3×3×64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.

Systems and techniques for implementing an energy-efficient multiplier-accumulator include generating symbols for a product of multiplications based on a corresponding set of multiplicands and multipliers, and generating an offset value based on a number of negative symbols in the generated symbols. Bit-by-bit negation is selectively performed on each product of the multiplications based on the generated symbols, and after performing the selective bit-by-bit negation, each product resulting from the multiplications is summed. The offset value is added to a final result of the summing based on a number of negative symbols in the generated symbols. Prior to the multiplication, one or more of the multiplicand and the multiplier are converted to a signed magnitude representation.

A latency processing unit is provided. A latency processing unit according to one embodiment includes: a plurality of MAC (Multipliers-Accumulators) trees that perform matrix multiplication operations for at least one partition among a plurality of partitions that realize an artificial intelligence model; simplified memory access that connects each of the plurality of MAC trees to a high-bandwidth memory storing the at least one partition through a plurality of channels; a vector execution engine that performs additional operations on the calculation results of the plurality of MAC trees; a local memory unit that stores the calculation results and activation values ​​of the vector execution engine; and an instruction word scheduling unit that schedules operations of the plurality of MAC trees and the vector execution engine.

The invention discloses a reconfigurable digital filter based on an FPGA (Field Programmable Gate Array), which comprises an FPGA chip, and the FPGA chip comprises an ROM (Read Only Memory) module, an RAM (Random Access Memory) module, a multiplier, an accumulator, a pulse counter, a filtering control module and a reconfiguration interface, the inertial device comprises at least one gyroscope and an accelerometer, and the gyroscope and the accelerometer both output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts count values of the N channels into floating-point numbers after the counting period is ended, and stores the floating-point numbers into the RAM module; the filtering control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, multiplexes the same group of computing resources to process signals of N channels in series, and completes filtering calculation according to an IIR filter algorithm; the reconfiguration interface can adjust the order and coefficient of the IIR filter online. The filter replaces DSP filtering, the FPGA resource utilization rate is increased, the chip cost is reduced, the execution efficiency of an inertial navigation system is improved, and online reconstruction can be carried out to adapt to different filtering requirements.

A self-attention mechanism calculation method, array (100), device (200) and system (400), and a computer-readable storage medium (500). The self-attention mechanism calculation array (100) comprises a plurality of multiplier accumulators (10). The self-attention mechanism calculation method comprises: calculating, by means of the plurality of multiplier accumulators (10), an intermediate tensor on the basis of a feature tensor and a weight tensor; and calculating, by means of the plurality of multiplier accumulators (10), a result tensor on the basis of the intermediate tensor.

A storage device and a method of operating the storage device are provided. The storage device includes a non-volatile memory device having a plurality of memory cells and a storage controller. Each memory cell is configured as one of a plurality of memory cell states, wherein different subsets of the plurality of memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in a memory cell in a first state, performs a multiplier-accumulator (MAC) operation on the data, and configures the memory cell as a second state corresponding to the result of the MAC operation to perform an in-situ update.

A complementary deep neural network accelerator includes: an accumulator array spiking neural network array processing module; a multiplier-accumulator convolutional neural network processing module; a highest RISC controller responsible for controlling the spiking neural network processing module and the convolutional neural network processing module, and processing an activation function and batch normalization; an attention module; and a neural network operation allocator.