7 results about "Multiplier accumulator" patented technology

A method and apparatus for deep learning are disclosed. The apparatus for deep learning includes a processor configured to support a plurality of different operation modes, the processor including a systolic array having a plurality of multiplier accumulator (MAC) units, and a control circuit configured to control a selection operation of the plurality of MAC units and a data movement between the plurality of MAC units, respectively, for each of the plurality of different operation modes.

Systems and techniques for implementing an energy-efficient multiplier-accumulator include generating symbols for a product of multiplications based on a corresponding set of multiplicands and multipliers, and generating an offset value based on a number of negative symbols in the generated symbols. Bit-by-bit negation is selectively performed on each product of the multiplications based on the generated symbols, and after performing the selective bit-by-bit negation, each product resulting from the multiplications is summed. The offset value is added to a final result of the summing based on a number of negative symbols in the generated symbols. Prior to the multiplication, one or more of the multiplicand and the multiplier are converted to a signed magnitude representation.

A latency processing unit is provided. A latency processing unit according to one embodiment includes: a plurality of MAC (Multipliers-Accumulators) trees that perform matrix multiplication operations for at least one partition among a plurality of partitions that realize an artificial intelligence model; simplified memory access that connects each of the plurality of MAC trees to a high-bandwidth memory storing the at least one partition through a plurality of channels; a vector execution engine that performs additional operations on the calculation results of the plurality of MAC trees; a local memory unit that stores the calculation results and activation values ​​of the vector execution engine; and an instruction word scheduling unit that schedules operations of the plurality of MAC trees and the vector execution engine.

The invention discloses a reconfigurable digital filter based on an FPGA (Field Programmable Gate Array), which comprises an FPGA chip, and the FPGA chip comprises an ROM (Read Only Memory) module, an RAM (Random Access Memory) module, a multiplier, an accumulator, a pulse counter, a filtering control module and a reconfiguration interface, the inertial device comprises at least one gyroscope and an accelerometer, and the gyroscope and the accelerometer both output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts count values of the N channels into floating-point numbers after the counting period is ended, and stores the floating-point numbers into the RAM module; the filtering control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, multiplexes the same group of computing resources to process signals of N channels in series, and completes filtering calculation according to an IIR filter algorithm; the reconfiguration interface can adjust the order and coefficient of the IIR filter online. The filter replaces DSP filtering, the FPGA resource utilization rate is increased, the chip cost is reduced, the execution efficiency of an inertial navigation system is improved, and online reconstruction can be carried out to adapt to different filtering requirements.

A self-attention mechanism calculation method, array (100), device (200) and system (400), and a computer-readable storage medium (500). The self-attention mechanism calculation array (100) comprises a plurality of multiplier accumulators (10). The self-attention mechanism calculation method comprises: calculating, by means of the plurality of multiplier accumulators (10), an intermediate tensor on the basis of a feature tensor and a weight tensor; and calculating, by means of the plurality of multiplier accumulators (10), a result tensor on the basis of the intermediate tensor.

A storage device and a method of operating the storage device are provided. The storage device includes a non-volatile memory device having a plurality of memory cells and a storage controller. Each memory cell is configured as one of a plurality of memory cell states, wherein different subsets of the plurality of memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in a memory cell in a first state, performs a multiplier-accumulator (MAC) operation on the data, and configures the memory cell as a second state corresponding to the result of the MAC operation to perform an in-situ update.