Convolution operation chip and communication equipment

A convolution operation and convolution technology, which is applied in the field of convolution operation chips and communication equipment, can solve the problem of increasing the number of RAM accesses, and achieve the effects of reducing RAM access pressure, reducing the number of RAM accesses, and reducing power consumption

Active Publication Date: 2017-06-13
HUAWEI MACHINERY
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AI Technical Summary

Problems solved by technology

Therefore, there is a large amount of duplicate data being input from RAM to the MAC array, which will increase the number of RAM accesses

Method used

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  • Convolution operation chip and communication equipment
  • Convolution operation chip and communication equipment
  • Convolution operation chip and communication equipment

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Experimental program
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Embodiment Construction

[0043] Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0044] figure 1 It is an application scene diagram of the convolution operation chip according to the embodiment of the present invention. In a typical communication device, such as a system on chip (System on Chip, "SoC"), the hardware architecture includes a central processing unit (Central Processing Unit, "CPU") 100, a double-rate synchronous DRAM (Double Date Rate SDRAM, referred to as "DDR SDRAM") 200 and the convolution operation chip 300 described in the embodiment of the present invention. CPU 100, DDR SDRAM 200 and convolution operation chip 300 are connected in communication. The CPU 100 controls the convolution operation chip 300 to start the convolution operation, and the DDRSDRAM 200 is used to input a plurality of convolution data and a plurality of convolution parameters to the data cache module of the convolution operation chip 300, and then t...

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Abstract

The invention provides a convolution operation chip and communication equipment. The convolution operation chip comprises an M*N multiplier accumulator array, a data cache module and an output control module; the M*N multiplier accumulator array comprises a first multiplier accumulator window, and a processing unit PE<X, Y> of the first multiplier accumulator window is used for conducting multiplication operation on convolution data of the PE<X, Y> and convolution parameters of the PE<X, Y> and transmitting the convolution parameters of the PE<X, Y> to PE<X, Y+1> and transmitting the convolution data of the PE<X, Y> to PE<X-1, Y+1> to serve as multipliers of multiplication operation between the PE<X, Y+1> and the PE<X-1, Y+1>; the data cache module is used for transmitting the convolution data and the convolution parameters to the first multiplier accumulator window; the output control module is used for outputting a convolution result. According to the convolution operation chip and the communication equipment, the RAM access frequency can be decreased and the RAM access stress can be relieved while the array resource utilization rate is increased.

Description

technical field [0001] This application relates to the field of artificial intelligence, and more specifically, to a convolution operation chip and communication equipment. Background technique [0002] Deep Neural Networks (DNN for short) technology has become a representative algorithm in the field of artificial intelligence. Key technologies such as character recognition, image classification or speech recognition based on deep neural network technology have been widely used in search engines and intelligence products such as mobile phones. Among them, the most effective and widely used neural network algorithm is the convolutional neural network (Convolutional Neural Network, "CNN") algorithm, referred to as "convolution operation". In the prior art, the core computing unit of the CNN algorithm is the multiply-add operation, and the multiplication accumulator (Multiplication Accumulator, referred to as "MAC") array is often used for matrix multiplication, and the convol...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/15
CPCG06F17/153G06F7/5443G06F7/57G06N3/045
Inventor 徐斌袁宏辉何雷骏
Owner HUAWEI MACHINERY
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