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Symbol extension method and structure of multipliers

A technology of extended structure and multiplier, which is applied in calculations using number system representations, calculations using non-contact manufacturing equipment, etc., and can solve problems such as increasing critical paths and affecting performance

Active Publication Date: 2005-12-07
ALICORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method can indeed reduce the waste of chip area in actual application, but there is an additional layer of correction columns, which means that the critical path will increase, which will affect performance.

Method used

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  • Symbol extension method and structure of multipliers
  • Symbol extension method and structure of multipliers
  • Symbol extension method and structure of multipliers

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Embodiment Construction

[0038]In the operation of the multiplier (multiplier) in the digital signal processor (DSP), the present invention provides a sign extension method and structure of the multiplier so that the area of ​​the sign extension bit (sign extension bit) of the digital signal processor chip does not increase , but also to maintain performance, but also to make the Wallace Tree ladder table less, and thereby reduce the critical path (critical path).

[0039] In the present invention, the sign extension bits generated by the partial product terms in the modified Booth algorithm are all set to 1 (one-extension), and the fixed values ​​can be summed up first in the calculation , and then judge whether there is a need for compensation, please refer to the schematic diagram of the symbol extension in Figure 2A, in which there are four groups of partial product terms, namely a, b, c, d, etc., in the improved Booth The first ladder-type bit table is formed in the algorithm, and the right side ...

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Abstract

This invention discloses a sign extension method and a structure of a multiplier, which designs multiple complement bits in the codes of sign extension during the code operation used in a multiplier of a DSP without increasing critical paths to reach the aim of reducing the waste to the chip area and reducing the size of the multiplier.

Description

technical field [0001] The invention relates to a sign extension method and structure of a multiplier. By setting a plurality of compensations in the code of the multiplier, the purpose of reducing wasted chip area and making the multiplier smaller is achieved. Background technique [0002] The multiplier (multiplier) is a basic operand component. A large number of complex operations almost always use the multiplier. The most typical operation in the digital signal processor (Digital Signal Processor, DSP) is the multiplier accumulator (Multiplier Accumulator, MAC) It is also necessary to use a multiplier. Multipliers are widely used in digital signal processing. For example, digital filters are the most typical example. In addition, most microprocessors today are also equipped with more than one multiply-accumulator MAC. The operation of multiplication and addition can be completed within one instruction time. [0003] Generally speaking, a modified Booth Algorithm is used...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 罗宇诚
Owner ALICORP
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