Floating point multiply-add, accumulate unit with exception processing

Abstract

A Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard is described with exception handling. Operations including exception handling in a way that does not interfere with execution of data flow operations, overflow detection, zero detection and sign extension are adopted for 2's complement and Carry-Save format.

Description

REFERENCE TO PRIORITY APPLICATIONS[0001]This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 17 / 397,241 filed on 9 Aug. 2021, which application claims the benefit of U.S. Provisional Patent Application Nos. 63 / 190,749 filed 19 May 2021, No. 63 / 174,460 filed 13 Apr. 2021, No. 63 / 166,221 filed 25 Mar. 2021, and No. 63 / 165,073 filed 23 Mar. 2021, which applications are incorporated herein by reference; and benefit of U.S. Provisional Patent Application No. 62 / 239,384, filed 31 Aug. 2021 is also claimed, which application is incorporated herein by reference.FIELD OF THE DISCLOSURE[0002]The field of the disclosure is implementation of arithmetic logic circuits, including floating point, multiply-add-accumulate circuits, also sometimes referred to as multiply and accumulate circuits, for high speed processors, including processors configured for efficient execution of training and inference.BACKGROUND OF THE DISCLOSURE[0003]Arithmetic logic circuits, i...

AI Technical Summary

Benefits of technology

The solution enables fast execution of floating-point operations with exception handling, preventing system failures and improving performance by completing operations without interruptions, even when encountering illegal or unsupported results, thus enhancing the reliability and efficiency of complex mathematical computations.

Problems solved by technology

Arithmetic logic circuits, including floating point, multiply-and-accumulate units, as implemented in high performance processors, are relatively complicated logic circuits.

In data flow architectures, and other architectures executing complex algorithms such as machine learning algorithms, these exceptions can cause the algorithms to stall or fail.

Exceptions in real time systems that cause algorithms to stall or fail can result in system failures or other problems in performance.

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