Floating point multiply-add, accumulate unit with exception processing

a technology of multiplying and accumulating units and logic circuits, applied in the field of implementation of arithmetic logic circuits, can solve problems such as system failures or other problems in performance, algorithms to stall or fail, and relatively complicated logic circuits,

Active Publication Date: 2022-09-29
SAMBANOVA SYST INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Arithmetic logic circuits, including floating point, multiply-and-accumulate units, as implemented in high performance processors, are relatively complicated logic circuits.
In data flow architectures, and other architectures executing complex algorithms such as machine learning algorithms, these exceptions can cause the algorithms to stall or fail.
Exceptions in real time systems that cause algorithms to stall or fail can result in system failures or other problems in performance.

Method used

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  • Floating point multiply-add, accumulate unit with exception processing
  • Floating point multiply-add, accumulate unit with exception processing
  • Floating point multiply-add, accumulate unit with exception processing

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Embodiment Construction

[0050]A detailed description of a technology implementing an arithmetic unit for a configurable, and reconfigurable, data flow architecture with exception handling is provided. An example reconfigurable data flow architecture is described in U.S. Pat. No. 10,831,507, by Shah et al., issued Nov. 10, 2020, which is incorporated by reference as if fully set forth herein. The arithmetic unit can execute a plurality of floating point arithmetic operations using input operands and generating at least one output operand, where the source of the input operands, the destination of the output operand and the operation are configurable, and reconfigurable by configuration data that can be static during a data flow operation.

[0051]In the execution of at least one of the floating point arithmetic operations, exceptions related to illegal operations and to generation of results not normally represented in the floating point encoding format utilized are detected, and results of the operation are s...

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Abstract

A Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard is described with exception handling. Operations including exception handling in a way that does not interfere with execution of data flow operations, overflow detection, zero detection and sign extension are adopted for 2's complement and Carry-Save format.

Description

REFERENCE TO PRIORITY APPLICATIONS[0001]This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 17 / 397,241 filed on 9 Aug. 2021, which application claims the benefit of U.S. Provisional Patent Application Nos. 63 / 190,749 filed 19 May 2021, No. 63 / 174,460 filed 13 Apr. 2021, No. 63 / 166,221 filed 25 Mar. 2021, and No. 63 / 165,073 filed 23 Mar. 2021, which applications are incorporated herein by reference; and benefit of U.S. Provisional Patent Application No. 62 / 239,384, filed 31 Aug. 2021 is also claimed, which application is incorporated herein by reference.FIELD OF THE DISCLOSURE[0002]The field of the disclosure is implementation of arithmetic logic circuits, including floating point, multiply-add-accumulate circuits, also sometimes referred to as multiply and accumulate circuits, for high speed processors, including processors configured for efficient execution of training and inference.BACKGROUND OF THE DISCLOSURE[0003]Arithmetic logic circuits, i...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F7/544G06F7/483
CPCG06F7/5443G06F7/483
Inventor OKLOBDZIJA, VOJIN G.KIM, MATTHEW M.
Owner SAMBANOVA SYST INC
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