Arithmetic circuit, arithmetic processing device, and arithmetic processing method

A technology for computing circuits and circuits, which is applied in the field of arithmetic circuits, and can solve the problems of arithmetic circuit logic quality limitations, difficult subtraction and shift-type arithmetic circuits, etc.

Inactive Publication Date: 2011-01-05
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to such time constraints, it is difficult to find defects in subtraction and shift type arithmetic circuits by logic simulation
Therefore conventionally, the improvement of the logic quality of arithmetic circuits has been limited

Method used

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  • Arithmetic circuit, arithmetic processing device, and arithmetic processing method
  • Arithmetic circuit, arithmetic processing device, and arithmetic processing method
  • Arithmetic circuit, arithmetic processing device, and arithmetic processing method

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Embodiment Construction

[0022] Embodiments are described below with reference to the drawings, wherein like numerals refer to like elements throughout.

[0023] figure 1 An arithmetic circuit according to the first embodiment is illustrated. figure 1 The arithmetic circuit includes a register 1 , a preprocessing circuit 2 , a solution prediction circuit 3 , an intermediate value calculation circuit 4 , a solution generation circuit 5 and an error detection circuit 6 .

[0024] figure 1 Register 1 in represents one or more registers. The register 1 stores an intermediate value 1a generated by the intermediate value calculation circuit 4 and an extension sign 1b added to the intermediate value 1a by sign extension of the intermediate value 1a.

[0025] The processing circuit 2 stores in the register 1 one or more values ​​on which an arithmetic operation is to be performed. For example, the preprocessing circuit 2 stores the dividend in the register 1 when the register 1 performs division or stores...

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Abstract

In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.

Description

technical field [0001] Embodiments discussed herein relate to an arithmetic circuit, an arithmetic processing device, and an arithmetic process. Background technique [0002] Arithmetic logic circuits include adder-subtractors, dividers, square root calculators, and more. Techniques for performing division and square root calculation by using an electronic circuit include a restoring algorithm, a nonrestoring algorithm, an SRT (Sweeney-Robertson-Tocher) algorithm, and the like. In these arithmetic algorithms, an operation of n digits for obtaining a quotient or a square root is repeated, where n is a natural number. The arithmetic algorithm described above has a feature in that the total number of digits of the quotient or the square root is proportional to the number of repetitions of the above operation. Since subtraction and bit shifting are repeated in the above-mentioned arithmetic algorithm as in calculations on paper, the above-mentioned arithmetic algorithm is here...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/18G06F7/57
CPCG06F7/535
Inventor 鸭志田志郎
Owner FUJITSU LTD
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