9 results about "Barrel shifter" patented technology

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

The application discloses a random rotation DEM structure for reducing switch activity, comprising a digital-to-analog converter, a digital input of the digital-to-analog converter is divided into an input code and a random rotation number, the random rotation number is input into a switch activity reduction structure through a barrel shifter output result delayed by a D flip-flop for one period, a feedback output of the switch activity reduction structure is fed back to the barrel shifter as an input, and an output of the barrel shifter after rotation controls corresponding switches and is connected to a corresponding cell array. The application uses input data to replace a pseudo-random number generator, and uses relatively simple logic to realize a switch activity reduction function, so that the complexity is reduced.

The invention provides a configurable parallel coding and decoding circuit and method suitable for a post quantum cryptography algorithm. The configurable parallel coding and decoding circuit comprises a register group, a barrel type shifter and a buffer control module, the register group is used for caching multiple groups of input unequal-bit-width data and recording currently cached effective data bits; the barrel type shifter is connected with the register group and is used for carrying out shifting alignment operation on the data cached in the register group to generate output data with standard bit width; the buffer control module is connected with the register group and the bucket shifter, and dynamically configures a parallel processing path according to an algorithm mode selection signal and a coding mode signal; and based on the effective data bits recorded in the register group, the shift amount required by the bucket shifter is automatically calculated, and the time sequence of data input and output is controlled, so that the problem that the encoding and decoding circuit cannot meet diversified bit width and parallelism requirements is solved.

The invention belongs to the technical field of semiconductors, and particularly provides a barrel type shifter based on ferroelectric field effect transistors, which comprises at least one alternative multiplexer, the alternative multiplexer comprises an N-type ferroelectric field effect transistor and a P-type ferroelectric field effect transistor, and the N-type ferroelectric field effect transistor is connected with the P-type ferroelectric field effect transistor. A drain electrode of the N-type ferroelectric field effect transistor and a source electrode of the P-type ferroelectric field effect transistor are connected to serve as an input end, a source electrode of the N-type ferroelectric field effect transistor and a drain electrode of the P-type ferroelectric field effect transistor are connected to serve as an output end, and grid electrodes of the N-type ferroelectric field effect transistor and the P-type ferroelectric field effect transistor are connected and connected with a master control signal; according to the invention, the adjustable threshold voltage and non-volatile storage characteristics of a ferroelectric field effect transistor (FeFET) are utilized, the left shift, right shift or cyclic shift function of any digit is realized in a single clock period, the number of transistors required in a traditional structure is effectively reduced, work under zero gate voltage is supported, and the circuit area and static power consumption are effectively reduced.

The invention discloses a self-adaptive hyperdimensional computing (HDC) accelerator supporting incremental learning, and belongs to the technical field of artificial intelligence hardware acceleration. The accelerator comprises a feature extraction and coding circuit, an incremental prototype-like storage resource pool, a parallel reasoning array and a confidence perception retraining circuit. Wherein the incremental prototype-like storage resource pool comprises a pre-allocated BRAM array and a write enable gating logic, and class expansion during operation is realized through logic-physical address decoupling; the confidence perception retraining circuit is integrated with a double-threshold comparator group and a barrel-shaped shift scaling circuit without a multiplier, and monitors the minimum Hamming distance in real time through a hardware comparator and drives a barrel-shaped shifter to dynamically generate an update weight. According to the method, low-overhead incremental learning is realized on the premise that hardware does not need to be synthesized again through resource isolation and adaptive weight adjustment of a pure hardware level, the disastrous forgetting phenomenon is effectively inhibited, and the retraining efficiency is remarkably improved.

This invention provides a configurable hardware architecture and bit manipulation method based on Banyan networks, belonging to the fields of digital logic circuits and high-performance computing technology. The invention aims to solve the problems of high hardware overhead, high power consumption, and long latency caused by the need for separate hardware modules—a Banyan network and a barrel shifter—to achieve combined bit-gathering and cyclic shifting operations in existing technologies. The architecture of this invention includes a Banyan network switching module and a control signal generation module. The control signal generation module generates an offset prefix count by superimposing the cyclic shift amount *r* with the original prefix count based on a bit mask, and uses this count to generate control signals for each stage of the Banyan network via an LROTC circuit. Through innovative modifications to the Banyan network control logic, this invention enables a single network to simultaneously perform both advanced bit operations, bit-gathering and cyclic shifting. This invention offers significant advantages such as hardware resource savings, reduced power consumption, improved performance, flexible design, and easy expansion, and can be widely applied in processor design, cryptographic acceleration, digital signal processing, and other fields.

The present application relates to the technical field of digital integrated circuit and processor design, in particular to a multi-precision / mixed-precision fusion multiply-add calculation unit circuit.The present application starts from four aspects: a Booth multiplier array with bit width adaptive mapping, a reconfigurable compressor array, a configurable barrel shifter with high hardware multiplexing, and an asymmetric reconfigurable binary tree composed of a leading zero detector;and the four modules are used to realize multi-precision data type support from low precision (INT4, INT8, FP8, FP16, BF16) to high precision (FP32), and the calculation precision is maximally preserved during mixed-precision calculation;compared with the traditional FMA unit designed separately for different precisions, the present application greatly optimizes the hardware multiplexing rate and energy efficiency ratio on the basis of supporting multi-precision / mixed-precision calculation mode, improves the energy efficiency ratio and calculation throughput, and is suitable for artificial intelligence accelerators, general-purpose processors and high-performance computing chips.

The application discloses a kind of antilog conversion equipment and method, it is related to data processing technical field, main purpose is to solve the problem of high delay of existing shift scheme, low data processing efficiency.It includes: barrel shifter group, data selector, addition unit and negation unit, wherein the barrel shifter group includes left shift barrel shifter and right shift barrel shifter, the input end of the right shift barrel shifter is connected with the output end of the negation unit, and the input end of the left shift barrel shifter is connected with the output end of the addition unit;The input end of the data selector is respectively connected with the output end of the left shift barrel shifter, the output end of the right shift barrel shifter and shift number end, for data selection, output data conversion result.

The invention discloses a double-path protection approximate multiplier for neural network acceleration. According to the method, multiplication is decomposed into addition operation of an index and a mantissa on the basis of the McCheer logarithm principle, and the design comprises three parts, namely a decomposition unit, a parallel addition unit and a reconstruction unit; wherein the parallel addition unit comprises an index path and a mantissa path, the index path adopts an approximate triple modular redundancy addition structure, and high-reliability fault tolerance is realized through three parallel addition modules and a majority voter; and a mantissa path adopts a truncation self-detection adder structure, truncation calculation is performed on high effective bits, and fault detection and result switching are performed based on structural invariants, so that lightweight fault tolerance is realized. And the reconstruction unit combines the results of the exponential path and the mantissa path through a barrel-shaped shifter, and outputs an approximate product result. The area and power consumption can be remarkably reduced, high reliability and high efficiency are both achieved, and the method is suitable for scenes such as neural network acceleration and safety-critical calculation.