19 results about "Registered memory" patented technology

The invention relates to the technical field of photography data processing, in particular to a large-volume oblique photography data visualization loading method and system, and the method comprises the steps: obtaining OSGB format original data; during preprocessing, grids are divided according to spatial scales, OSGB files of low-level LOD are merged into 3DTiles by an octree, an index is generated, and after surface features are semantically segmented by AI, simplification is carried out according to engineering requirements; the dynamic LOD scheduling comprises the steps of dividing an octree into multiple layers of tiles, screening visible tiles through a view cone, filtering shielding through ray detection, and slicing pixel errors; storing the data in a register-memory-SSD-HDD four-level cache by using an LRU-K strategy; performing GPU rendering on SSD data, and adjusting LOD according to a feedback load; the system comprises a data preprocessing module, a dynamic LOD processing module, a distributed cache module and a renderer module which cooperatively realize efficient loading. The problems that in an existing oblique photography data loading technology, static LOD adaptation is poor, data blocks are single, storage hierarchies are insufficient, and the video memory utilization rate is low are solved.

Embodiments of the present application provide a storage optimization method, device, equipment and storage medium, comprising: obtaining an initial configuration of a memory manager, the memory manager being used for managing a remote direct memory access memory pool, modifying the initial configuration to modify registered memory used by the remote direct memory access memory pool into storage performance development kit memory, obtaining storage data of the remote direct memory access memory pool, transmitting the storage data to a plurality of preset buffers of a non-volatile memory interface device, obtaining memory data including the storage data in the plurality of preset buffers, and judging the source of the memory data in any preset buffer, if the memory data in the preset buffer is from the storage performance development kit memory, submitting the memory data in the preset buffer to a storage performance development kit non-volatile memory interface driver, and the embodiments of the present application improve system performance.

This application relates to a convolution optimization operation method, apparatus, computer device, and storage medium. The method includes: acquiring feature map data in global memory; inputting the current original feature map into a DepthWise convolution model for a first core operation to obtain a first intermediate feature map, and loading the first intermediate feature map into shared memory; splitting the first intermediate feature map to obtain multiple second intermediate feature maps, and loading each second intermediate feature map into register memory; inputting each second intermediate feature map into a PointWise convolution model for a second core operation to obtain the current result feature map data, and loading the current result feature map data into global memory; and iteratively processing the next original feature map adjacent to the current original feature map as the current original feature map until all result feature map data is obtained. Using the embodiments of this application, separable convolution operations can be accelerated.

The invention relates to a vector segment memory access instruction processing method and device. Comprising the following steps: decoding a vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in an instruction operation code of the vector segment memory access instruction and configuration information of a vector control state register; splitting the macro operation capable of being dispatched into a plurality of micro operations according to the size of each vector element and the effective vector length; calculating the memory access byte number and the memory access address of each micro-operation; and executing each micro-operation according to the memory access byte number and the memory access address of each micro-operation. According to the embodiment of the invention, the address and the size of the memory access data of each register are calculated through a standardized calculation formula by taking the elementary as the granularity, so that the dependence among the registers is reduced, and logic resources required by data processing are reduced.

Stacked registers having different ferroelectric memory element configurations are disclosed. Apparatuses and methods for managing data in processing systems, such as but not limited to data storage devices such as solid state drives (SSDs). A ferroelectric stacked register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first configuration and a second arrangement of FMEs of a different second configuration, the first and second arrangements being arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide a pointer to each of the respective cache lines based on a time sequence of operations of the processor. Data sets can be migrated into the different arrangements as needed by the controller based on different operational characteristics of the respective FME configurations. The FMEs can be non-volatile and read-disturbive. Refresh circuitry can be selectively implemented in different operational modes.

Aspects of the disclosed technology include techniques and mechanisms for partial dot product reduction using customized temporary memory. The custom temporary memory may be a dedicated memory that is dedicated to receive and store the partial dot product determined by the matrix multiplier unit. Each partial dot product may correspond to a tile of a resulting matrix, where the resulting matrix is a product of matrix multiplications that may use a first matrix representing a user query as a left operand, and a second matrix representing a user query as a right operand. And using a second matrix representing a trained model containing data available to respond to the user query as a right side operand. The custom register memory may append tiles determined by matrix multiplication, where the appended tiles may create a resulting matrix. Customized temporary memory may write the resulting matrix to general purpose memory, where the resulting matrix may be used to respond to a user query.

The application relates to the technical field of distributed computing and memory management, and discloses a memory dynamic resource allocation and scheduling method for big data system integration, which comprises the following steps: analyzing a distributed computing job to establish a mapping of a data block logical address to a local page table entry; generating an event notification when a downstream operator completes reading of the data block; writing data in a local physical page frame into a registered memory area of a remote computing node through RDMA, and constructing a remote memory index table in a kernel state; writing a remote redirection mark and an integer index, and releasing the corresponding local physical page frame; when a target page table entry triggers a page fault exception and contains the redirection mark, the system acquires a remote data address according to the integer index by querying the index table, pulls the remote data to update the page table entry, and restores process execution. The application effectively releases local memory resources, realizes on-demand recovery of remote data through a page fault exception mechanism of an operating system, and reduces system recalculation overhead.

A homomorphic processing unit (HPU) (200) may accelerate homomorphic processing operations governed by a homomorphic encryption scheme. The HPU may access encrypted operands from memory, wherein an encrypted operand represents an encryption of unencrypted data by the homomorphic encryption scheme, wherein the encrypted operand is represented by a set of ciphertext words. The HPU may include a controller (205) to access instructions for operations to be performed on encrypted operands and convert them into micro-instructions for operations to be performed on ciphertext words. The HPU may further comprise a register memory (209) and multiple execution units that may be invoked in parallel by executing micro-instructions. The execution units may include a load / store unit (207) for transferring ciphertext words, an arithmetic logic unit (210) for performing arithmetic operations, and at least one ciphertext transformation unit (211, 212) configured to modify ciphertext words in compliance with the homomorphic encryption scheme.

The optical module provided by the invention comprises a circuit board, a CDR chip, a laser driving chip, a laser chip and an MCU. The laser driving chip internally comprises a first register and a second register. A register value is stored in the first register, and the register value in the first register is used for representing the working state of the CDR chip. When the MCU responds to the register value representing that the CDR chip is in the lock losing state in the first register, the MCU writes the register value into the second register value, and the register value in the second register is used for adjusting output of the laser driving chip to the CDR chip. And the laser driving chip responds to the register value in the second register, outputs a control instruction to the CDR chip, and further adjusts the phase of the clock signal output by the CDR chip until the phase of the clock signal output by the CDR chip and the phase of the electric signal input to the CDR chip accord with a preset relationship, so that locking and recovery of the electric signal are realized. And adjusting the CDR chip to a locking state.

The invention provides a distributed database incremental backup method based on RDMA, and belongs to the technical field of distributed databases. Incremental data needing to be backed up are accurately positioned through an incremental data detection module of a database main node in combination with a dual recognition mechanism of data block check value comparison and transaction log LSN number marking, and the backup efficiency is improved. Resource waste of total data transmission is avoided; an RDMA reliable connection transmission mode is adopted, so that a backup node can directly access a registered memory area where incremental data of a main node is located, multiple rounds of data copying are omitted, and a database main node CPU does not need to participate in a transmission process; meanwhile, a continuity verification module based on an LSN number is deployed at a backup node, the integrity of received data can be verified in real time, and if data missing exists, rapid supplementary transmission is conducted through RDMA connection, and the integrity of backup data is guaranteed. And the backup task and the user service task have no resource competition, so that an efficient, low-consumption and reliable incremental backup solution is provided for the distributed database.

The invention provides a multi-head attention task accelerator mapping configuration generation method and system. The multi-head attention task accelerator mapping configuration generation method comprises the steps of obtaining operator common parameters, head dimensions and key sequence lengths of multi-head attention tasks; obtaining the total capacity of a shared memory and the total capacity of a register of the space accelerator; constructing shared memory overhead and register memory overhead based on the operator shared parameters, the head dimension and the key sequence length; constructing a shared memory overhead constraint based on the shared memory overhead and the total capacity of the shared memory; constructing a register memory overhead constraint based on the register memory overhead and the total capacity of the register; setting a block factor corresponding to each task parameter in the operator common parameters as a block factor minimum value, and executing a constraint range step to obtain a block factor range corresponding to each task parameter; and obtaining an initial mapping space according to the block factor range, and searching under a preset reinforcement learning algorithm based on the initial mapping space to generate an optimal mapping configuration. According to the invention, the generation efficiency of the optimal mapping configuration can be improved.

The present disclosure discloses a process hard interrupt method and related device, a breakpoint address is written in advance in a process control block of the process, the hard interrupt method comprises: when the process is scheduled to a running state, obtaining the breakpoint address from the process control block; writing the obtained breakpoint address into an emptied debug address register, so that a debug unit executes a hard interrupt based on the breakpoint address stored in the debug address register during running of the process. The present disclosure enables the processor to execute the hard interrupt on the single process even if the scontext is not set in the debug unit.

The invention provides a resource access authority management method and device. The resource access permission management method comprises the steps that under the condition that an access request sent to a target chip by a target host through an external debugger is received, the permission state of the target chip is acquired, and the access request is used for requesting to access system resources of the target chip; under the condition that the permission state is a permission locking state, performing permission identification on the target host; and forwarding the access request to a system bus in the target chip under the condition that the authentication result of the permission authentication is passed, so as to access system resources through the system bus. By means of the resource access authority management method, damage or information leakage of system resources (such as a register and a memory area) caused by access of an unauthorized host is effectively avoided, the risk that software programs in the system resources are maliciously tampered is reduced, and system safety is improved.

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

This application provides a method and system for elastic scaling of a distributed cache pool, including: obtaining the amount of free memory on a node, and determining regions to be contributed or reclaimed based on a comparison with high-water mark or low-water mark thresholds; performing handle operations through a handle pool interface to obtain pre-allocated fast-registered memory handles for regions to be contributed and update their mappings, and clearing the mappings of regions to be reclaimed and returning them; when a region to be contributed is only used for remote read cache data, selecting handles with at least remote read permissions and immediately pushing them into the pool, setting a recalculation tolerance window for regions to be reclaimed, adjusting the aging period and the number of fixed-retain handles according to the reclamation step size; and updating the global address mapping table to complete vertical scaling. This application utilizes cache recalculation to relax handle attribute matching conditions, replaces RDMA silent waiting with a recalculation tolerance window, and links the aging period with the reclamation step size to achieve fine-grained high-frequency elastic scaling.

The invention discloses a memory reuse method, device and equipment for a temporary memory and a storage medium, and the method comprises the steps: obtaining an artificial intelligence operator program containing the storage demand of the temporary memory, carrying out the activity analysis of a plurality of input data blocks associated with the temporary memory in the operator program, and obtaining the life cycle of each data block; judging whether an input data block with a dynamic shape exists in the operator program or not; if yes, inserting a main control code containing memory multiplexing logic of each data block in an operator program compiling stage, and completing memory multiplexing of the temporary memory according to the main control code; and if not, according to the life cycle of each data block, generating a temporary memory allocation and reuse strategy in an operator program compiling stage, and completing the memory reuse of the temporary memory. According to the technical scheme provided by the embodiment of the invention, the time cost and the labor cost consumed by manually allocating the memory resources of the temporary storage can be avoided, the allocation difficulty of the memory resources of the temporary storage is reduced, and the memory utilization rate of the temporary storage is improved.

This invention relates to the field of data transmission technology, providing a data transmission method, apparatus, electronic device, storage medium, and program product. The method includes: initializing resources required for RDMA, wherein the initialization process includes: creating registered memory for RDMA; creating multiple work queue pairs according to different data transmission logics of the target data packets to be transmitted, each work queue pair corresponding to a data transmission logic; dividing the data buffer in the registered memory into memory blocks of predetermined size; writing the target data packets to be transmitted into the data buffer in units of memory blocks; selecting the corresponding target work queue based on the data transmission logic of the target data packets to be transmitted; sending the target data packets to be transmitted in the data buffer to the peer, or receiving data from the peer into the data buffer. This invention selects different work queue pairs as logical channels for data transmission according to different data transmission logics to complete the operation, enabling parallel transmission of multiple data packets and reducing transmission latency.

Methods and systems for managing access to a memory device of a data processing system that is shared between a plurality of abstracted resources hosted on the data processing system are disclosed. A memory device may have a secured portion storing information that is used to authenticate requests from the plurality of abstracted resources for accessing the shared memory device. Access to and modification of the secured portion of the shared memory device is granted only to a management entity of the data processing system. The management entity registers memory address ranges of the memory device allocated to each of the plurality of abstracted resources in the secured portion. The management entity uses the registered memory address ranges to verify memory device access requests from the plurality of abstracted resources.

Disclosed are a CPU capable of quickly processing a memory copy instruction and a method therefor, the CPU comprises: an instruction decoder, a general-purpose register, a memory copy controller, a bus interface, a buffer, an adder and a comparator, the memory copy controller comprises a state machine, the state machine comprises an idle state, a read state and a write state, and in the idle state, the instruction decoder waits for receiving a valid memory copy instruction; in the read state, data of a source address are read through the bus interface and the data are temporarily stored in the buffer; and in the write state, the temporarily stored data from the buffer are written to a target address through the bus interface, the adder is used for updating the address, and the comparator is used for judging whether memory copy is finished.