106 results about "Registered memory" patented technology

Internal variables generated by a compiler are assigned to machine resources such as registers and memory by the resource assigning unit 11, and when the assembler code generation unit 18 has outputted an instruction sequence, the alias accessibility analyzing unit 19 registers memory access instructions in the instruction sequence in the assigned resource information 14 according to whether the instructions have a possibility of access by alias. The assembler code optimization unit 20 refers to the assigned resource information 14 and performs optimization at assembler level, thereby reducing the program size and execution time of the instruction sequence.

A system and method is provided to improve software simulation. A software emulator is used in conjunction with a hardware simulator. A special snapshot instruction is included in the software code that is emulated. When the snapshot instruction is encountered, values such as register, memory, and program stack values, are stored creating an initial snapshot. Code continues to be emulated and, when the next snapshot instruction is encountered, the values are written to create a second snapshot. The initial values are used to set an initial state in a hardware model that is simulated on a hardware simulator. The results of the hardware simulation are compared to the second snapshot to uncover software errors and/or hardware errors so that the software can be modified or the hardware design can be modified. Multiple sets of snapshots can be taken to analyze multiple sections of the software program.

A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Method and system are provided where a memory key structure is used for authenticating access to a memory location that is registered for a remote direct memory access (RDMA) operation. The memory key structure not only includes a standard memory key that is expected by an RDMA enabled network interface card (RNIC), but also includes an endpoint network address identifier and a transport identifier. The endpoint network address identifier and the transport identifier are verified before an entity is granted access to the registered memory location.

An input method and a system for querying by using at least one region formed by at least one enclosed track are provided. The method mainly includes: forming at least one region on digital type information; storing at least one of text information and image information in the track into a registering memory; generating at least one of text-based information retrieval and image-based information retrieval according to the at least one of the text information and the image information; and finally, transmitting the at least one of the text-based information retrieval and the image-based information retrieval to at least one search engine for querying.

The invention belongs to the field of computer figures, and provides a modeling structure of a GPU texture mapping non-blocking memory Cache. The modeling structure comprises a texture Cache storage status and control unit (1), a missing information status handling register memory cell (MSHR) (2), a multi-request combination and collision detection unit (3), and a texture memory Cache core unit (4). Hardware modeling with accurate periods is conducted on a texture memory Cache access process, parallel processing of texture access request data is realized through a multi-process mode including input request collision detection, request combination and division, multiple ports, multiple Banks and non-blocking flowing, and large-scale parallelism and high throughput demands of texture access data are met effectively. Moreover, the modeling structure effectively avoids configuration of complex circuit signal design and rapid assessment large-scale hardware system, is suitable for system level design and development of circuits in an early age, and provides effective reference for products and functions of the same kind.

Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

An emergency notification system and method that is operable to provide a technique for a user to transmit an emergency signal request wherein the emergency signal request is transmitted to a 911 operations center, registered EMS providers, and at least one named contact identified by the user transmitting the emergency signal request simultaneously. The emergency notification system includes a server database having control software and further includes a software application for mobile devices. The emergency notification system is operable to receive and store relevant medical data for each of the registered users of the system wherein the medical data is transmitted to emergency medical service providers during the transmission of the emergency signal request. A customized notification message is additionally sent to a predefined list of contacts during the emergency signal request. The customized notification message further includes the geographic coordinates of the user transmitting the emergency signal request.

The invention discloses a microprocessor and computer system, aims to provide a 32 bits media digital signal processor. The processor includes plastic processor core, flow control unit, command taking unit, commands, operation number reading, data, command high speed buffer, data high speed buffer, on-chip memory, universal register file, media register file, bus interface unit, system bus, integer executing unit, signal executing unit, media executing unit, arithmetic logic unit, barrel shifter, integer multiplier and adder, and by-pass unit and system control coprocessor. The media digital signal processor command structure in the invention can be divided into register-register command facing memory operation, and register-memory command facing to memory operation. It is good at executing system program, and executing digital signal processing program, it ha characters of RISC processor and DSP processor, it is an integral of the RISC and DSP system structures.

The invention discloses a hybrid PUF circuit, comprising a basic PUF circuit and a control PUF circuit, wherein a decision type PUF circuit achieves the basic PUF circuit, a register and an initial electrification value PUF circuit are alternately arranged to achieve the control PUF circuit, a control signal stored in the register and a signal generated by the initial electrification value PUF circuit are spliced to form n bits of excitation signals to serve as enabling signals of the basic PUF circuit, each bit of excitation signal needs to pass through two different delay paths composed of a first delay circuit unit and a second delay circuit unit in the basic PUF circuit, the output data of the basic PUF circuit are generated by a delay difference between the two delay paths, in the two delay paths, each delay circuit unit completes an on-off operation according to the corresponding excitation signal, determines to propagate a rising edge signal linearly or crosswise and finally generates a PUF output signal through a decision device; and the hybrid PUF circuit has the advantages of higher reliability and randomness and stronger model attack and machine learning attack resistance.

A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

The present invention discloses a simulator simulating special function register, comprising a simulation chip and a simulator processor. A general register is arranged inside the simulation chip, and when the simulator is in monitoring state, a microprocessor core of the simulation chip can automatically store a current reading/writing operation FIFO count pointer value of a SFR realized in the FIFO mode into the register. After the microprocessor core of the simulation chip executes reading/writing operation to the SFR, the microprocessor core can automatically update the value in the register. The simulator processor can automatically read the value stored in the register. The simulator processor can send commands or commands and data to the simulation chip, and the microprocessor core carries out reading/writing operation to the SFR. The present invention provides reliable and convenient means for debugging the SFR of the type, and can effectively improve the debugging efficiency of user programs.

A data converter and its converting method having both the functions of barcode technology and RFID technology, and conforming with related regulations of international civil aviation are disclosed. The data converter includes a barcode reading module, a processing module, and a reading module. The converting method includes the following steps: (1) Reading an external barcode data S_BC by the barcode reading module; (2) Reading the external barcode data S_BC read by the barcode reading module by the barcode reading module from a memory; (3) Reading the date data (preset data S_P) from the RTC (Real Time Clock) by the processing module; (4) Reading the data arrangement format defined within the firmware by the processing module; (5) Combining the external barcode data S_BC and the preset data S_P in accordance with the arranged format by the processing module; (6) Writing the combined data into a register memory by the processing module; (7) Starting the RFID module by the processing module; (8) Reading the combined data from the register memory by the processing module and writing into the RFID medium memory through the RFID module.

A motion vector (MV) prediction method and a prediction apparatus thereof are applicable for a video image encoder/decoder to predict an MV of a video image. Firstly, segment a macroblock in the video image into microblocks. Then, configure a row memory and three register memories to register the MV required for prediction. Finally, the MV stored in the row memory or the register memories at a position corresponding to the current microblock to be predicted is used to predict the MV of the current microblock to be predicted in the current macroblock to be predicted. After the prediction is completed and moved to another macroblock or microblock, the MV stored in the row memory or the register memories is updated according to a predetermined storage updating condition.

Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. At least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

The invention discloses a method for message communication based on an RDMA protocol. The method comprises the following steps of dividing a shared cache into a first preset number of memory blocks and registering a second preset number of memory blocks; judging whether the byte length of communication data is greater than the sum of the second preset number of memory blocks; if yes, registering a third preset number of memory blocks; storing the communication data into the registered memory blocks; and sending the communication data in the memory blocks to a receiving end. According to the method, the efficiency of sending the communication data is improved and the system resources are effectively saved; the invention also discloses a system for message communication based on the RDMA protocol, and the system has the beneficial effects.

The invention discloses a user attribute-based search realization method. The method comprises the following steps: S1, ordering registered users and recommending registered users which are ordered in front of a preset place according to attribute data of the registered users by utilizing a close frequency model (RFM); S2, constructing an index database according to the recommended result, searching matched available resource information in the index database according to key words in a search request when a search engines receives the search request of an accessor, and then displaying the available resource information corresponding to each registered user in turn. Correspondingly, the invention also discloses a user attribute-based search realization system. By the search realization method and the search realization system provided by the embodiment of the invention, the user attributes of the registered users can be embodied in the searched results of the available resource information, and the increment of search engine calculation time and the display delay of the results can be avoided.

The invention provides a design method for converting a PCI bus into an ISA bus or an APB bus. The design method solves the problem that in the prior art, a processor in an embedded type computer system cannot have access to devices meeting the ISA parallel bus protocol at the same time. According to the technical scheme, the design method comprises the steps that a PCI bus interface 1 receives a PCI bus configuration instruction of the PCI bus and sends the PCI bus configuration instruction to a PCI instruction analysis controlling module 2; the PCI instruction analysis controlling module 2 analyzes out a register address and a register memory address from the bus configuration instruction and sends the register address and the register memory address to a PCI bus configuration register module 3; the PCI bus configuration register module 3 writes the register address into a PCI control register which is located in the PCI bus configuration register module 3 and corresponds to the register address.