44 results about "Registered memory" patented technology

The invention relates to the technical field of data transmission, and provides a data transmission method and device, electronic equipment, a storage medium and a program product.The method comprises the steps that resources needed by RDMA are initialized, and the initialization process comprises the steps of creating a registration memory of the RDMA and creating a plurality of work queue pairs according to different data transmission logics of a target data packet to be transmitted, each work queue pair corresponds to one data transmission logic; dividing a data buffer area in the registered memory into memory blocks with preset sizes; writing the to-be-transmitted target data packet into a data buffer area by taking a memory block as a unit; and selecting the corresponding target working queue based on the data transmission logic of the to-be-transmitted target data packet, and sending the to-be-transmitted target data packet in the data buffer area to an opposite end, or receiving data of the opposite end to the data buffer area. According to different data transmission logics, different working queues are selected to complete operation on the logic channels serving as data transmission, multiple pieces of data are transmitted in parallel, and transmission delay is reduced.

Provided in the present disclosure are an RDMA-based data transmission method, and a device, a storage medium and a program product. During an RDMA connection establishment process, a local work queue used for same-host RDMA communication and a remote work queue used for cross-host RDMA communication are created at the same time, and a same-host recognition function is added. When same-host communication is recognized, the local work queue is used to directly execute a data copy operation in registered memories of two applications to replace a traditional RDMA transmission operation. Therefore, the compatibility with an RDMA programming interface and transparency or unawareness with regard to applications are achieved, the transmission delay between different RDMA applications on the same host can also be reduced, thereby reducing the consumption of a PCIe bandwidth, and ensuring the fairness in resource contention between local traffic and Internet traffic.

The invention discloses a synchronization method and device for storage metadata, electronic equipment and a storage medium, and relates to the technical field of computers, a consistent Hash algorithm is adopted to realize mapping of data fragments and storage nodes, a monitoring node maintains the relation, a data change event is directionally sent to a corresponding partition, and the data change event is stored in the corresponding partition. Meanwhile, the Bloom filter is used for pre-checking events to filter invalid information, only local related changes are processed, the check value is transmitted, and the memory area is pre-registered, so that the data interaction mode between the nodes is optimized, and the defects of a full-connection mode are avoided; the technical problems that in an existing block storage metadata synchronization mechanism, due to the fact that a full connection mode is not optimized for node scale extension, the network connection number is increased in an exponential level mode, the system overhead is increased, and the cluster expansion capacity is limited can be solved, and the purposes of reducing the system overhead, improving the cluster expansion capacity and improving the cluster expansion efficiency are achieved. And the performance of the distributed block storage system is optimized.

A fault-recoverable firmware detection system and method, a storage medium, and a server. The method comprises: acquiring target fault information stored in a fault register, and sending the target fault information to a BMC (201); upon receiving the target fault information sent by a BIOS, the BMC analyzing the target fault information, and determining a fault type (202); when the fault type of the target fault information is a recoverable fault, the BMC controlling a virtual external device to send a target heartbeat request to a server operating system according to a preset sending period, and receiving response data fed back by the server operating system on the basis of the target heartbeat request (203); and within a preset duration during which the BMC sends the target heartbeat request to the server operating system, if an interruption occurs in the response data fed back by the operating system, determining that the server operating system is crashed, and on the basis of the target fault information, determining a faulty component in a server (204).

The invention discloses an industrial control system data transmission method and device based on RDMA, and belongs to the technical field of communication. According to the method, an RDMA transmission engine is used in the data information transmission process between a sender and a receiver, and a data buffer area is preset in the sender in advance, so that a network card can directly write in or read the buffer area specified by a user in the data transmission process, and unnecessary overhead in the data transmission process is reduced; according to the method, the memory registration area cache is introduced into the RDMA transmission engine, so that registered memory resources can be reused, the number of times and expenditure of memory registration are reduced, and the overall performance of the RDMA is improved.

The invention provides a memory access method and device, electronic equipment and a storage medium, and the method comprises the steps: determining registered memories of a first network card and a second network card, building connection between a client and a distributed server through the first network card and the second network card, responding to a remote access request of the server, obtaining a destination address corresponding to a target server, and sending the destination address to the server; determining a target node, connected with the client, of the target server and a registered memory of a network card corresponding to the target node, dividing the first data block into a preset number of target data blocks and erasure verification blocks, and copying the target data blocks and erasure verification blocks to the registered memory of the network card corresponding to the target node, and reading the target data block and the erasure verification block of the registered memory through the target server, and writing the second data block to be returned to the client into the registered memory. According to the invention, the network card is ensured to only operate the memory with good affinity, the network communication efficiency in distributed storage is improved, and the memory access effectiveness of the distributed storage system is improved.

The invention relates to the technical field of computer security, in particular to a security isolation management system based on virtualization, which comprises a virtual machine intrusion behavior monitoring module, a Hypervisor monitoring system call frequency and a network connection request of a target virtual machine, and obtaining an intrusion behavior feature matching event. According to the method, the system calling frequency and the network connection request are monitored in real time when the target virtual machine runs, the intrusion behavior characteristics are captured, the targeted alarm instruction is generated, the memory of the target virtual machine is subjected to copy-on-write snapshot when the threat behavior is triggered, and the memory state at the intrusion moment is completely stored; establishing a new virtual processor context, and dynamically redirecting a network socket associated with an attack session to realize immediate isolation and transparent shunting of intrusion behaviors; and further, taking the data entering the memory as a taint source starting point, and tracking a flow path of a data taint among a register, a memory address and a process file handle.

A system, method, and apparatus for in-run camera image processing are provided that configure a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing a plurality of camera image frame sequences having different specified exposures to detect a complete set of frames having a first common frame number from the camera image frame sequences; identifying, from the sequence of image frames, an effective combination of different exposures having a second common frame number following the first common frame number; and processing the effective combination of the different exposures from the first and second sequences of camera image frames to generate output data from the ISP pipeline.

The embodiment of the invention provides a storage optimization method and device, equipment and a storage medium, and the method comprises the steps: obtaining the initial configuration of a memory manager, the memory manager is used for managing a remote direct memory access memory pool, and the initial configuration is modified, modifying a registered memory used by the remote direct memory access memory pool into a memory of a storage performance development kit, acquiring storage data of the remote direct memory access memory pool, and transmitting the storage data to a plurality of preset buffer areas of the nonvolatile memory interface equipment, the method comprises the following steps: acquiring memory data including storage data in a plurality of preset buffer areas, and judging a source of the memory data in any preset buffer area; and if yes, submitting the memory data in the preset buffer area to a nonvolatile memory interface driver of a storage performance development kit. According to the embodiment of the invention, the system performance is improved.

A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

The invention provides a data transmission method and device, equipment and a storage medium. The method comprises the steps that a first edge CDN node directly stores to-be-transmitted data received from a source client in a first memory area; the first memory area is determined by the first edge CDN node according to a registered memory area indicated in a first connection parameter issued by the scheduling server; the first edge CDN node reads the to-be-transmitted data from the first memory area and sends the to-be-transmitted data to a second edge CDN node, and the second edge CDN node is used for directly storing the to-be-transmitted data in a second memory area, reads the to-be-transmitted data from the second memory area and sends the to-be-transmitted data to a destination client; the second memory area is determined by the second edge CDN node according to a registered memory area indicated in a second connection parameter issued by the scheduling server; wherein the first edge CDN node and the second edge CDN node are determined in the at least one edge CDN node by the scheduling server according to a data transmission service request sent by the source client.

The invention discloses a memory register, a memory register access method, a memory register access device and a medium, the memory register comprises an M * N Bank array formed by a plurality of SRAM Banks, M and N are integers greater than zero, each row in the Bank array comprises a plurality of Banks for storing the same data, and addresses corresponding to the plurality of Banks for storing the same data are the same; each Bank corresponds to a plurality of addresses, and the Banks in different rows correspond to different addresses; the Bank array corresponds to a plurality of read data channels and a plurality of write data channels and is used for simultaneously performing read operation and write operation on a plurality of Banks in the Bank array. According to the technical scheme provided by the embodiment of the invention, the problem of Bank conflict when a plurality of data processing requests access the same Bank at the same time can be avoided, the output bandwidth of the register is fully utilized, and the processing efficiency of the data requests is improved.

A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

The invention relates to the technical field of photography data processing, in particular to a large-volume oblique photography data visualization loading method and system, and the method comprises the steps: obtaining OSGB format original data; during preprocessing, grids are divided according to spatial scales, OSGB files of low-level LOD are merged into 3DTiles by an octree, an index is generated, and after surface features are semantically segmented by AI, simplification is carried out according to engineering requirements; the dynamic LOD scheduling comprises the steps of dividing an octree into multiple layers of tiles, screening visible tiles through a view cone, filtering shielding through ray detection, and slicing pixel errors; storing the data in a register-memory-SSD-HDD four-level cache by using an LRU-K strategy; performing GPU rendering on SSD data, and adjusting LOD according to a feedback load; the system comprises a data preprocessing module, a dynamic LOD processing module, a distributed cache module and a renderer module which cooperatively realize efficient loading. The problems that in an existing oblique photography data loading technology, static LOD adaptation is poor, data blocks are single, storage hierarchies are insufficient, and the video memory utilization rate is low are solved.

The invention provides an RDMA (Remote Direct Memory Access) communication method based on user mode Ethernet data transmission, which comprises the following steps: in a user mode rDMA-core driver, defining an RDMA verbs operation structural body, establishing a mapping relationship between an RDMA verbs operation function and a DPDK API (Application Program Interface), mapping an RDMA operation to a DPDK data plane, and calling the DPDK API to realize the RDMA verbs operation function; when the network card queue is operated to send data, the RDMA sends a request to call the DPDK API, constructs a RoCEv2 protocol data packet, and sends the data packet to the network card; when the network card queue is operated to receive data, after a DPDK polling mode driver receives a data packet, the received data packet is analyzed according to the RoCEv2 protocol, effective data is written into a pre-registered memory, and a user mode is triggered to complete a queue event. The invention further provides an RDMA communication device based on the user mode Ethernet data transmission.

Embodiments of the present application provide a storage optimization method, device, equipment and storage medium, comprising: obtaining an initial configuration of a memory manager, the memory manager being used for managing a remote direct memory access memory pool, modifying the initial configuration to modify registered memory used by the remote direct memory access memory pool into storage performance development kit memory, obtaining storage data of the remote direct memory access memory pool, transmitting the storage data to a plurality of preset buffers of a non-volatile memory interface device, obtaining memory data including the storage data in the plurality of preset buffers, and judging the source of the memory data in any preset buffer, if the memory data in the preset buffer is from the storage performance development kit memory, submitting the memory data in the preset buffer to a storage performance development kit non-volatile memory interface driver, and the embodiments of the present application improve system performance.

This application relates to a convolution optimization operation method, apparatus, computer device, and storage medium. The method includes: acquiring feature map data in global memory; inputting the current original feature map into a DepthWise convolution model for a first core operation to obtain a first intermediate feature map, and loading the first intermediate feature map into shared memory; splitting the first intermediate feature map to obtain multiple second intermediate feature maps, and loading each second intermediate feature map into register memory; inputting each second intermediate feature map into a PointWise convolution model for a second core operation to obtain the current result feature map data, and loading the current result feature map data into global memory; and iteratively processing the next original feature map adjacent to the current original feature map as the current original feature map until all result feature map data is obtained. Using the embodiments of this application, separable convolution operations can be accelerated.

A method for executing instructions in a processor core implemented with a source operand collection cache coupled to at least one input of a data path located within the processor core, comprising the method: Decoding an instruction to determine a plurality of operands specified by the instruction, For each operand in the plurality of operands: Determine that the operand is not stored in the source operand collection cache, and load the operand from a local register into the source operand collection cache. Configuring the processor core to execute instructions on the operand stored in the source operand collection cache. Updating a cache table after the operand has been loaded into the source operand collection cache to associate a register index corresponding to the operand with a memory location in the source operand collection cache, determining which register indices to use as operands for the next instruction, to determine whether the register value corresponding to that register index is currently stored in the same memory location as a result of scheduling a previous instruction, and if the same memory location stores that register value, another register value from the same register bank is loaded into a different memory location during the same instruction cycle.

The invention relates to a vector segment memory access instruction processing method and device. Comprising the following steps: decoding a vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in an instruction operation code of the vector segment memory access instruction and configuration information of a vector control state register; splitting the macro operation capable of being dispatched into a plurality of micro operations according to the size of each vector element and the effective vector length; calculating the memory access byte number and the memory access address of each micro-operation; and executing each micro-operation according to the memory access byte number and the memory access address of each micro-operation. According to the embodiment of the invention, the address and the size of the memory access data of each register are calculated through a standardized calculation formula by taking the elementary as the granularity, so that the dependence among the registers is reduced, and logic resources required by data processing are reduced.

Stacked registers having different ferroelectric memory element configurations are disclosed. Apparatuses and methods for managing data in processing systems, such as but not limited to data storage devices such as solid state drives (SSDs). A ferroelectric stacked register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first configuration and a second arrangement of FMEs of a different second configuration, the first and second arrangements being arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide a pointer to each of the respective cache lines based on a time sequence of operations of the processor. Data sets can be migrated into the different arrangements as needed by the controller based on different operational characteristics of the respective FME configurations. The FMEs can be non-volatile and read-disturbive. Refresh circuitry can be selectively implemented in different operational modes.

Aspects of the disclosed technology include techniques and mechanisms for partial dot product reduction using customized temporary memory. The custom temporary memory may be a dedicated memory that is dedicated to receive and store the partial dot product determined by the matrix multiplier unit. Each partial dot product may correspond to a tile of a resulting matrix, where the resulting matrix is a product of matrix multiplications that may use a first matrix representing a user query as a left operand, and a second matrix representing a user query as a right operand. And using a second matrix representing a trained model containing data available to respond to the user query as a right side operand. The custom register memory may append tiles determined by matrix multiplication, where the appended tiles may create a resulting matrix. Customized temporary memory may write the resulting matrix to general purpose memory, where the resulting matrix may be used to respond to a user query.

The application relates to the technical field of distributed computing and memory management, and discloses a memory dynamic resource allocation and scheduling method for big data system integration, which comprises the following steps: analyzing a distributed computing job to establish a mapping of a data block logical address to a local page table entry; generating an event notification when a downstream operator completes reading of the data block; writing data in a local physical page frame into a registered memory area of a remote computing node through RDMA, and constructing a remote memory index table in a kernel state; writing a remote redirection mark and an integer index, and releasing the corresponding local physical page frame; when a target page table entry triggers a page fault exception and contains the redirection mark, the system acquires a remote data address according to the integer index by querying the index table, pulls the remote data to update the page table entry, and restores process execution. The application effectively releases local memory resources, realizes on-demand recovery of remote data through a page fault exception mechanism of an operating system, and reduces system recalculation overhead.

A homomorphic processing unit (HPU) (200) may accelerate homomorphic processing operations governed by a homomorphic encryption scheme. The HPU may access encrypted operands from memory, wherein an encrypted operand represents an encryption of unencrypted data by the homomorphic encryption scheme, wherein the encrypted operand is represented by a set of ciphertext words. The HPU may include a controller (205) to access instructions for operations to be performed on encrypted operands and convert them into micro-instructions for operations to be performed on ciphertext words. The HPU may further comprise a register memory (209) and multiple execution units that may be invoked in parallel by executing micro-instructions. The execution units may include a load / store unit (207) for transferring ciphertext words, an arithmetic logic unit (210) for performing arithmetic operations, and at least one ciphertext transformation unit (211, 212) configured to modify ciphertext words in compliance with the homomorphic encryption scheme.

The optical module provided by the invention comprises a circuit board, a CDR chip, a laser driving chip, a laser chip and an MCU. The laser driving chip internally comprises a first register and a second register. A register value is stored in the first register, and the register value in the first register is used for representing the working state of the CDR chip. When the MCU responds to the register value representing that the CDR chip is in the lock losing state in the first register, the MCU writes the register value into the second register value, and the register value in the second register is used for adjusting output of the laser driving chip to the CDR chip. And the laser driving chip responds to the register value in the second register, outputs a control instruction to the CDR chip, and further adjusts the phase of the clock signal output by the CDR chip until the phase of the clock signal output by the CDR chip and the phase of the electric signal input to the CDR chip accord with a preset relationship, so that locking and recovery of the electric signal are realized. And adjusting the CDR chip to a locking state.

Methods and systems for managing access to a memory device of a data processing system that is shared between a plurality of abstracted resources hosted on the data processing system are disclosed. A memory device may have a secured portion storing information that is used to authenticate requests from the plurality of abstracted resources for accessing the shared memory device. Access to and modification of the secured portion of the shared memory device is granted only to a management entity of the data processing system. The management entity registers memory address ranges of the memory device allocated to each of the plurality of abstracted resources in the secured portion. The management entity uses the registered memory address ranges to verify memory device access requests from the plurality of abstracted resources.

The invention provides a distributed database incremental backup method based on RDMA, and belongs to the technical field of distributed databases. Incremental data needing to be backed up are accurately positioned through an incremental data detection module of a database main node in combination with a dual recognition mechanism of data block check value comparison and transaction log LSN number marking, and the backup efficiency is improved. Resource waste of total data transmission is avoided; an RDMA reliable connection transmission mode is adopted, so that a backup node can directly access a registered memory area where incremental data of a main node is located, multiple rounds of data copying are omitted, and a database main node CPU does not need to participate in a transmission process; meanwhile, a continuity verification module based on an LSN number is deployed at a backup node, the integrity of received data can be verified in real time, and if data missing exists, rapid supplementary transmission is conducted through RDMA connection, and the integrity of backup data is guaranteed. And the backup task and the user service task have no resource competition, so that an efficient, low-consumption and reliable incremental backup solution is provided for the distributed database.

The invention provides a multi-head attention task accelerator mapping configuration generation method and system. The multi-head attention task accelerator mapping configuration generation method comprises the steps of obtaining operator common parameters, head dimensions and key sequence lengths of multi-head attention tasks; obtaining the total capacity of a shared memory and the total capacity of a register of the space accelerator; constructing shared memory overhead and register memory overhead based on the operator shared parameters, the head dimension and the key sequence length; constructing a shared memory overhead constraint based on the shared memory overhead and the total capacity of the shared memory; constructing a register memory overhead constraint based on the register memory overhead and the total capacity of the register; setting a block factor corresponding to each task parameter in the operator common parameters as a block factor minimum value, and executing a constraint range step to obtain a block factor range corresponding to each task parameter; and obtaining an initial mapping space according to the block factor range, and searching under a preset reinforcement learning algorithm based on the initial mapping space to generate an optimal mapping configuration. According to the invention, the generation efficiency of the optimal mapping configuration can be improved.

Provided in the embodiments of the present application are a data processing method, a cloud storage system and an electronic device. The method is applied to a first network device, wherein the first network device comprises a first application layer, a first user mode protocol stack and a first network interface controller, the first application layer comprising a first application program. The method comprises: using a first application layer to allocate, from a first registered memory space of a first network interface controller, a first target memory block to data to be sent of a first application program; using the first application layer to write said data into the first target memory block; using the first application layer to call a first user mode protocol stack, so as to encapsulate said data in the first target memory block; and using the first network interface controller to send said encapsulated data in the first target memory block. The method provided in the embodiments of the present application can shorten delay and is CPU-scheduling-friendly, thereby improving the system processing performance.

The present disclosure discloses a process hard interrupt method and related device, a breakpoint address is written in advance in a process control block of the process, the hard interrupt method comprises: when the process is scheduled to a running state, obtaining the breakpoint address from the process control block; writing the obtained breakpoint address into an emptied debug address register, so that a debug unit executes a hard interrupt based on the breakpoint address stored in the debug address register during running of the process. The present disclosure enables the processor to execute the hard interrupt on the single process even if the scontext is not set in the debug unit.

The invention provides a resource access authority management method and device. The resource access permission management method comprises the steps that under the condition that an access request sent to a target chip by a target host through an external debugger is received, the permission state of the target chip is acquired, and the access request is used for requesting to access system resources of the target chip; under the condition that the permission state is a permission locking state, performing permission identification on the target host; and forwarding the access request to a system bus in the target chip under the condition that the authentication result of the permission authentication is passed, so as to access system resources through the system bus. By means of the resource access authority management method, damage or information leakage of system resources (such as a register and a memory area) caused by access of an unauthorized host is effectively avoided, the risk that software programs in the system resources are maliciously tampered is reduced, and system safety is improved.