Modeling structure of GPU texture mapping non-blocking memory Cache

A technology of texture mapping and texture storage, which is applied in processor architecture/configuration, image data processing, image memory management, etc. It can solve problems such as limited data bandwidth and data processing speed, graphics elements, and texture data cannot be fully loaded, and achieve Avoid circuit signal design and avoid cumbersome effects

Active Publication Date: 2017-05-17
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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AI Technical Summary

Problems solved by technology

In view of the large amount of computation in 3D graphics rendering and the need to process tens of thousands of vertex or pixel data, in order to achieve real-time rendering of 3D graphics on mobile devices, the graphics processing system is required to have a very fast processing speed, b...

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  • Modeling structure of GPU texture mapping non-blocking memory Cache
  • Modeling structure of GPU texture mapping non-blocking memory Cache
  • Modeling structure of GPU texture mapping non-blocking memory Cache

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Embodiment

[0042] The technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0043] Such as figure 1 , figure 2 and image 3 As shown, a GPU texture mapping non-blocking rate storage Cache modeling structure uses SystemC language and Transaction Level Modeling (TLM, transaction level modeling) method to perform cycle-accurate hardware modeling on the texture storage Cache access process. The texture mapping unit includes 4 functional modules. These 4 functional unit models adopt the multi-process method of input request conflict detection, request merging and division, multi-port, multi-Bank, and non-blocking pipeline to realize parallel processing of texture access request data.

[0044] The texture mapping non-blocking storage Cache unit includes a texture Cache storage state and control unit (1), a missing information state holding register storage unit (MSHR) (2), a multi-requ...

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Abstract

The invention belongs to the field of computer figures, and provides a modeling structure of a GPU texture mapping non-blocking memory Cache. The modeling structure comprises a texture Cache storage status and control unit (1), a missing information status handling register memory cell (MSHR) (2), a multi-request combination and collision detection unit (3), and a texture memory Cache core unit (4). Hardware modeling with accurate periods is conducted on a texture memory Cache access process, parallel processing of texture access request data is realized through a multi-process mode including input request collision detection, request combination and division, multiple ports, multiple Banks and non-blocking flowing, and large-scale parallelism and high throughput demands of texture access data are met effectively. Moreover, the modeling structure effectively avoids configuration of complex circuit signal design and rapid assessment large-scale hardware system, is suitable for system level design and development of circuits in an early age, and provides effective reference for products and functions of the same kind.

Description

technical field [0001] The invention belongs to the field of computer graphics, in particular to a SystemC modeling structure of GPU texture mapping non-blocking rate storage Cache (high-speed buffer memory). Background technique [0002] With the rapid development of graphics, in addition to a large number of applications in personal computers and workstations, 3D graphics technology has also made great progress in embedded fields such as mobile phones and car navigation. In view of the large amount of calculation in 3D graphics rendering and the need to process tens of thousands of vertex or pixel data, in order to achieve real-time rendering of 3D graphics on mobile devices, the graphics processing system is required to have a very fast processing speed, but the storage of mobile devices, etc. The capacity is effective, a large number of primitives and texture data cannot be fully loaded, and frequent interaction with external memory is required. The limited data bandwidt...

Claims

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Application Information

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IPC IPC(8): G06T15/00G06T1/60G06T1/20
CPCG06T1/20G06T1/60G06T15/005
Inventor 田泽魏美荣吴晓成许宏杰郑新建魏艳艳
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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