32-bit media digital signal processor

Abstract

The invention discloses a microprocessor and computer system, aims to provide a 32 bits media digital signal processor. The processor includes plastic processor core, flow control unit, command taking unit, commands, operation number reading, data, command high speed buffer, data high speed buffer, on-chip memory, universal register file, media register file, bus interface unit, system bus, integer executing unit, signal executing unit, media executing unit, arithmetic logic unit, barrel shifter, integer multiplier and adder, and by-pass unit and system control coprocessor. The media digital signal processor command structure in the invention can be divided into register-register command facing memory operation, and register-memory command facing to memory operation. It is good at executing system program, and executing digital signal processing program, it ha characters of RISC processor and DSP processor, it is an integral of the RISC and DSP system structures.

Description

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AI Technical Summary

Benefits of technology

This patented technology allows for efficient processing of complicated mathematical calculations without slowing down their overall speed due to limitations imposed on its timing or flow rate. It achieves this by performing certain types of computations more efficiently than traditional methods that require multiple steps like addition/subtraction between two numbers.

Problems solved by technology

This patented describes how modern electronic devices handle increasingly larger quantities of data faster without sacrificing efficiency. It suggests combining both registers and directives into a smaller space called RAM instead of relying upon older architectures like CRAM. Additionally, the patents discusses the use of advanced technology nodes like LSI circuits and logic processes to enhance overall functionality and reduce resource usage compared to previous designs. Overall these technical problem addressed by the patented proposals includes developing efficient algorithms for handling large volumes of data efficiently within limited computing environments, reducing circuit size and optimizing programmable code implementation, simplifying data transferring between modules, minimizing redundancy, enhancing programmability, implementing dynamic load-and-store relationships, providing flexibility in adaptively changing operational settings based on demand, meeting demands over long periods of time, and supporting highly optimized function requests across numerous domains.

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