The invention discloses a low power consumption compact digital decimation filter for a CMOS image sensor. The low power consumption compact digital decimation filter comprises a ripple counter, a bit-by-bit inversion module BWI, an adder and a 13-bit register, and an inverter and the bit-by-bit inversion module BWI are arranged in front of the adder, the output data bit width of the ripple counter is 7 bit and is half of the output data bit width of the register; an meanwhile, the register only needs 13 bits to realize a 13-bit dynamic range. In practice, since the output data bit width of the ripple counter is 7 bit and is half of the output data bit width of the register, the number of inverters and selectors is reduced by half compared to the original. Meanwhile, the structure guarantees that the register data will not have the problem of data overflow, so the register only needs 13 bits to realize the 13-bit dynamic range without overflowing the data bit register. The low power consumption compact digital decimation filter disclosed by the invention adopts a special structure of pre-BWI, which greatly reduces the number of filter transistors, reduces the power consumption andreduces the cost.