36 results about "Bit inversion" patented technology

Devices, systems, and methods for improving performance of a non-volatile memory are described. An example method includes generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory, and then generating a circular shift flip sequence based on the inversion seed and a flip sequence. The method further includes performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence, processing the intermediate bit sequence to generate an output bit sequence, and finally, writing the output bit sequence to a page in the non-volatile memory. In this example, the page that the output bit sequence is written (or programmed) to is of the page type for which the inversion seed and circular shift flip sequence are generated.

The invention relates to the field of integrated circuit design, and discloses a processor preamble and mantissa continuous bit parallel counting device and method. The device comprises a 32-bit bit sequence flipping module, a 32-bit bit negation module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module and a 32-bit result output module. According to the invention, parallel counting can be carried out on leading zeros, leading 1, mantissa zeros or mantissa 1 of various data with different precisions in a single processor clock period, so that the required time sequence path length is greatly shortened, the higher processor clock frequency is realized, the multiplexing of a hardware circuit is realized, and the cost is reduced. The circuit greatly reduces the use of transistor resources, reduces the area of a chip, reduces the cost and power consumption of the chip, improves the operation efficiency, universality and adaptability of the processor, and is suitable for being applied to application scenes such as a high-performance digital signal processor and a CPU (Central Processing Unit).

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

Disclosed are a data inversion encoding circuit, an eFLASH memory device and an operation method thereof. The data inversion encoding circuit includes a count and comparison circuit, receiving data with plural bits, counting numbers of 0 and 1 in the bits, and outputting a selection signal when number of 0 is larger than number of 1; an inverter, receiving the data and outputting bit inversion data; and a selection circuit, receiving the data and the bit inversion data, and selecting the data or the bit inversion data based on the selection signal. The bit inversion data is output when number of 0 is larger than number of 1.

The application discloses a hardware accelerator and an acceleration method based on a full homomorphic encryption isomorphism mapping, and the accelerator comprises a polynomial storage area, a Tag and Sel reloading unit, a read address calculation unit, a permutation network and a cache unit. The method comprises the following steps: according to the architecture parallelism configured during compilation and the maximum polynomial degree to be supported, after compilation, the isomorphism mapping of the polynomial can be completed according to the actual polynomial degree and the isomorphism parameter of the input. The embodiment of the application can reduce the domain conversion overhead and the overhead of the bit inversion arrangement coefficient, and reduce the calculation burden of the homomorphic rotation. The application can be widely applied to the field of homomorphic encryption technology.

The application discloses a spectrum extraction method and device of fast Fourier transform, and a computer storage medium, and the method comprises the following steps: adopting inverse sequence output calculation for a front-stage FFT operation, performing linear spectrum processing and logarithmic amplitude operation on a calculation result to obtain an amplitude frequency point; grouping the amplitude frequency point to obtain an amplitude grouping matrix of a preset grouping number; adopting a radix-2 butterfly operation structure to adjust a road number of the amplitude grouping matrix, and storing the amplitude grouping matrix in a sequence after the road number adjustment; dividing the stored amplitude grouping matrix to obtain an amplitude frequency point matrix; marking the position of an element in the amplitude frequency point matrix, performing a binary bit inversion operation on the marked position to obtain a rearranged position; adjusting the position sequence of the element according to the rearranged position to obtain an amplitude frequency point rearranged matrix, and obtaining a spectrum after completing spectrum sequence arrangement and FFTShift operation through serial-parallel conversion. The method realizes parallel sequence arrangement operation of large-point-number spectrum data.

The application discloses a data processing system, method, electronic equipment and storage medium, and relates to the technical field of computers. The original input data is preprocessed into multiple groups of target input data through a data input module, and is input into multiple iteration calculation units to obtain to-be-calculated data and an encoding identifier. When the encoding identifier indicates that the to-be-calculated data needs to be pre-inverted, the to-be-calculated data is pre-inverted to obtain to-be-calculated inverted data. The subsequent iteration calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result. That is, the iteration calculation unit only needs to perform a small amount of data bit inversion on the to-be-calculated inverted data through target calculation to obtain the data processing result. The number of times of data bit inversion in target calculation is reduced, dynamic inversion power consumption is reduced, and, compared with the power consumption reduction mode in the related art, the application does not need high-difficulty chip back-end layout and wiring, and can guarantee the performance and power consumption reduction effect of the chip.

Techniques for number theoretic transform (NTT) and inverse number theoretic transform (iNTT) are described. In some examples, an NTT circuit is to use a decimation-in-frequency (DIF) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order. In some examples, an iNTT circuit is to use a decimation-in-time (DIT) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order.

The present invention relates to a sampling apparatus and method robust against side-channel attacks, the method comprising the steps of: (a) receiving a random bit; (b) setting an iteration loop index i to 0 and determining whether the random bit is greater than or equal to NRCDT[i]; (c) if the random bit is greater than or equal to NRCDT[i], an adjustment value in an i-th iteration loop is set to 1, and if the random bit is smaller than NRCDT[i], the adjustment value in the iteration loop is set to 0; (d) updating a random integer by subtracting the adjustment value from 18; and (e) repeating steps (b) to (d) while increasing i by 1 until i reaches 17, thereby obtaining a finally updated random integer, wherein NRCDT[i] has a value obtained by bit-inverting RCDT[i] of a base sampler.

A method for operating a wireless power transfer system is configured for utilizing software for the purposes of thermal mitigation, via re-encoding data in a bitstream for data communicated in-band of wireless power transfer. The data is encoded as binary messages and, during a message of the bit stream, if the number of high pulses is greater than the number of low pulses, then the message is inverted, such that each of the high pulses of the message invert to a low pulse and each of the low pulses of the message invert to a high pulse. Thus, the data signals will always have 50% or less low pulses in the bit stream.

The application discloses an LDPC decoder and a method and device for early termination of decoding of the LDPC decoder and a medium, and relates to the technical field of LDPC code decoding. The method comprises the following steps: performing multiple decoding iteration processes on to-be-decoded data, and obtaining a corresponding error code word at the end of each decoding iteration process; calculating the to-be-decoded data and the error code word based on a preset bit inversion number calculation formula to obtain a bit inversion number at the end of each decoding iteration process; when a first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, obtaining an original error bit number estimation value by estimation according to the first bit inversion number, the second bit inversion number and the third bit inversion number; and when the original error bit number estimation value is greater than a preset threshold, early termination of decoding is performed. The early termination of decoding strategy can be optimized based on the original error bit number estimation value, and the early termination of decoding can be more flexibly and efficiently realized.

The invention relates to the field of data storage, and provides an FPGA program double-area backup method, device and equipment based on SPI FLASH and a medium. The method comprises the following steps: configuring a constraint file of an FPGA project, and generating a backup program bit stream file; a bootstrap program file is constructed, and the bootstrap program file is used for achieving address skipping in the loading process, so that the program skips to the initial position of the overtime loading program; constructing a loading timeout program file, wherein the loading timeout program file comprises timing logic and rollback triggering logic; integrating the boot program file, the backup program bit stream file and the loading timeout program file according to the storage address to obtain an integrated program file; and solidifying the integrated program file into an SPI FLASH, and establishing a double-region backup storage structure. According to the method, the problem that the system cannot be started due to bit reversal errors in long-term storage of the FPGA program is solved, and automatic switching and loading of the backup program are realized.

A system includes a series of first / second transceivers mutually coupled over data lanes as bidirectional transceivers, and first / second control logic coupled to the first / second transceivers, respectively. An encoding of bit inversions by the first / second control logic causes: first pair of transceivers coupled over a first data lane to transmit non-inverted bits in a first direction and a second direction over the first data lane; second pair of transceivers coupled over a second data lane to transmit inverted bits in a first direction but not a second direction over the second data lane; third pair of transceivers coupled over a third data lane to transmit inverted bits in the second direction but not the first direction over the third data lane; and fourth pair of transceivers coupled over a fourth data lane to transmit inverted bits in the first direction and the second direction over the fourth data lane.

The invention discloses a monitoring system based on an APB bus protocol, and solves the problems that in the prior art, only transmission termination and interruption report are supported, the hierarchical error processing capability is lacked, and the detailed context of an overtime event cannot be provided, so that troubleshooting is difficult. The monitoring system comprises a state monitoring unit used for tracking a bus transmission stage through a five-state machine; the dynamic CRC check engine unit is used for supporting 16 / 32-bit configurable polynomial and input and output bit inversion to obtain an updated CRC value and realize single-cycle byte processing; the multi-stage error early warning unit is used for identifying abnormal data in the slave equipment according to the updated CRC value and locking a fault address corresponding to the abnormal data; according to the monitoring system, complete unvarnished transmission of APB signals is achieved through the monitoring system of an APB bus protocol, and real-time monitoring and reliability guarantee of bus affairs are mainly achieved.

The application discloses an operation device and method based on non-0 starting non-cavity coding. By mapping all-0 coding to a non-zero reference value, using a negative number of inverse code, a full-field coding system without negative zero redundancy and coding cavity is constructed, and the bit-by-bit inversion and carry injection operations required by the traditional complement code are completely eliminated. Full-field coding can realize addition and subtraction operations only by switching the reference mirror image, and addition and subtraction have isomorphism, and the efficiency of multiplication and division operations is close, so that the iteration delay of division is significantly reduced. The application has the advantages of small hardware overhead, high operation efficiency, strong compatibility and expansibility, and is suitable for high-performance operation scenes such as CPU, GPU, AI accelerator, DSP and embedded processor.

A balun circuit addresses the bandwidth issue by using symmetric amplitude division and phase delay networks to convert single-ended signals to differential signals. Because the balun circuit's balance characteristics are guaranteed over a very wide bandwidth, other performance characteristics that can limit the operating bandwidth, such as impedance matching and insertion loss, can be carefully addressed without concern for amplitude and phase balance. A balun circuit splits a single-ended signal into four differential paths through symmetric networks and applies phase inversion by inverting the polarity of each differential path, thereby reducing the complexity, size, and loss of the balun circuit's overall configuration.

The application discloses a high-speed parallel CRC32 computing device and method based on FPGA. The device comprises a data preprocessing module, which is used for performing byte-by-byte bit inversion processing on input data when a data valid signal is valid; a dynamic bit width control module, which is used for acquiring total data length, recording remaining data length and outputting a valid byte number signal; a parallel CRC computing module, which is used for calling a CRC32 computing module with a corresponding bit width according to the valid byte number signal, performing parallel operation on the inverted data and outputting a CRC intermediate result; a result post-processing module, which is used for performing bit inversion and XOR processing on the intermediate result to generate a final check result; and a timing alignment module, which is used for controlling the output timing of a result valid signal through an internal delay counter. The application realizes high-speed parallel checking of any frame length and significantly reduces hardware resource occupation.

In a data processing apparatus 11, a buffer memory BM including a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2, stores therein data that is formed of a plurality of bits, and a CPU 11A reads the data from the buffer memory BM, performs bit inversion on the plurality of bits to generate bit inverted data in which a value of each of the bits is inverted, writes the bit inverted data in the buffer memory BM at a first time, reads the data from the buffer memory BM at a second time that is later than the first time, compares first data that is bit inverted data that is written in the buffer memory BM at the first time and second data that is bit inverted data that is read from the buffer memory BM at the second time, and determines presence of a failure in the buffer memory BM.

In a memory system (100, 100a), a memory controller issues a command including an extension flag field (F3) and a bank address field (F2) as a precharge command to a semiconductor memory device, the extension flag field (F3) specifying: which one of one, all, and two banks belonging to mutually different bank groups is precharged; and a second relative processing timing for the first bank in the case of two banks. In the case of two banks, the semiconductor memory device precharges the first bank determined by the bank address field, and precharges the second bank of a bank address obtained by inverting the inversion target bits in the bank address field at the relative processing timing.

This invention relates to a frequency tracking method for an ultrasonic transmitter, comprising the following steps: data acquisition, real-time synchronous acquisition of three signals: primary current, secondary current, and secondary voltage of a transformer; for each acquisition cycle, the acquired data is placed into the peripheral integrated control law accelerator coprocessor built into the main chip for Fourier transform, flipping the real and imaginary parts of the complex number, performing bit inversion, decompressing, and then performing Fast Fourier Transform (FFT) calculation to obtain the true Fourier series; the acquired waveform is reconstructed in the software to complete phase establishment; acquiring parameters such as amplitude, phase, phase difference between primary and secondary currents, phase difference between secondary voltage and current, phase difference between primary and secondary current and voltage, voltage, current, power, impedance, and frequency; frequency tracking is performed by sampling the target impedance; real-time sampling results in more timely signal feedback, improving the speed and accuracy of frequency tracking, ensuring operation within the working range, reducing the risk of oscillator damage, and lowering costs and risks.

The invention relates to the technical field of power electronics, in particular to a multiplier phase inversion suppression method for a continuous conduction mode PFC (Power Factor Correction) controller. The method comprises the following steps: extracting a characteristic parameter set of a target harmonic component from a sampling signal of a pin BO; acquiring a real-time voltage value of the pin VM, and storing the value as a previous sampling value; according to the characteristic parameter set and the previous sampling value, real-time compensation voltage used for restraining phase inversion is determined; injecting the real-time compensation voltage into a pin VM to obtain a corrected divider output voltage; the corrected divider output voltage acts on the multiplier so as to adjust the output current waveform of the multiplier; verifying whether the waveform polarity of the output current of the multiplier is in the same phase with the waveform polarity of the alternating current input voltage reflected by the bus voltage signal detected by the pin BO at the zero crossing point of the alternating current input voltage; if so, outputting a phase locking success signal; and if not, outputting a phase locking failure signal.

This invention relates to the field of integrated circuit design and discloses a parallel counting device and method for consecutive leading and mantissa bits in a processor. The device includes a 32-bit bit order reversal module, a 32-bit bit inversion module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module, and a 32-bit result output module. This invention enables parallel counting of leading zeros, leading ones, mantissa zeros, or mantissa ones for various data with different precisions within a single processor clock cycle. This significantly shortens the required timing path length, allowing for higher processor clock frequencies. It also enables hardware circuit reuse, greatly reducing transistor resource usage, chip area, chip cost, and power consumption. This improves the processor's operational efficiency, versatility, and adaptability, making it suitable for applications in high-performance digital signal processors and CPUs.

This application discloses a method, apparatus, and corresponding integrated circuit for mapping data to an integrated circuit processing core array, belonging to the field of integrated circuit technology. It includes: reversing and rearranging multiple input bits of an input array input to the integrated circuit to obtain a bit-inverted input array; determining an input bit mapping relationship reflecting the storage location of each inverted input bit in the bit-inverted input array within the processing core array based on the sequence of multiple input bits of the input array, the rearranged sequence of the inverted input bits of the bit-inverted input array, and a predetermined data storage method; storing each inverted input bit in the storage circuit of a corresponding different computing unit in the processing core array according to the input bit mapping relationship; and performing Fast Fourier Transform matrix multiplication calculations between multiple weight levels and the inverted input bits stored in the storage circuit of the computing unit in different computing units. This application can enhance the data processing capabilities of integrated circuits.

The application provides a storage device and a processing method for firmware exception of the storage device. The storage device comprises a flash memory and a main controller connected with the flash memory. The main controller comprises a static random storage unit and a central processing unit. The central processing unit is used for monitoring the running state of the storage device, reading part of test data from the flash memory and writing the test data into the static random storage unit when the running state of the storage device is in a firmware exception state, comparing the test data with the written data in the static random storage unit to obtain a normal detection result. The central processing unit is also used for performing bit inversion on the test data to obtain inverted data, writing the inverted data into the static random storage unit, comparing the inverted data with the written data in the static random storage unit to obtain an inverted detection result. The central processing unit is also used for generating exception detection information according to the normal detection result and the inverted detection result. The application can analyze the causes of the firmware exception of the storage device.

Embodiments of the present disclosure relate to dynamic bit inversion for reduced overhead DC balanced coding. A computed polarity bit controls whether or not bits are inverted and is inserted in the data stream whenever DC balancing is triggered. Fixed overhead codes are commonly used to provide DC balance. However, one can do much better than a fixed overhead code by observing that many data streams are inherently DC balanced, and a random data stream does not need a correction to its disparity every byte. For example, a string of alternating 1s and 0s is naturally DC balanced. The dynamic bit inversion code has the property that overhead is inserted only when needed. For a string of alternating 1s and 0s there is no overhead. In an example, the overhead is about 4%, about ⅓ that of a fixed overhead 8 bit / 9 bit code with the same maximum output disparity.

The invention provides a data inversion decoding circuit, an embedded memory device and an operation method thereof. The data inversion decoding circuit comprises a counting comparison circuit which receives data containing a plurality of bits, calculates the number of 0 and the number of 1 in the plurality of bits, and outputs a selection signal when the number of 0 is greater than the number of 1; an inverter receiving the data and outputting bit reversal data; the selection circuit receives the data and the bit reversal data, and selects the data or the bit reversal data according to a selection signal. When the number of 0 is greater than the number of 1, bit inversion data is output.

To provide an instrument capable of safely executing secret calculation by a person with simple operation.SOLUTION: A secret calculation instrument includes a plurality of input value components whose states of front and back are associated with 0 and 1. The plurality of input value components can be combined in a state in which the front and back cannot be distinguished. A combined structure in which the plurality of input value components are combined is configured to be reflection-symmetrical with respect to a reference line, and the front and back cannot be distinguished. An observation state is defined by randomly rotating, in an invisible state, the combined structure in an input state that is arranged in a state in which the input value component indicates an input value or bit inversion of the input value and in a state in which the front and back are concealed. An output state is defined by observing the front and back of the predetermined input value components in the observation state and inverting the front and back of the combined structure by reflection conversion with respect to a reference line based on observation results. In the output state, a state of the predetermined input value component is defined as an output value of a logical calculation.SELECTED DRAWING: Figure 2

A signal processing apparatus includes a storage processing part to perform processing on data represented in a second representation format, wherein the second representation format, while for a non-negative value identical to two's complement representation, for a negative value, has a representation format where (D−N−1) bits of the data of D-bits in the two's complement representation are bit-wise inverted, the (D−N−1) bits located between MSB and N consecutive lower bits including LSB, the storage processing part including a normalization circuit with a maximum exponent calculation circuit and a shift circuit to normalize a plurality of pieces of data represented in the second representation format for each block.

The present application provides a memory data repair method applied to an electronic device to repair data of a flash memory. The electronic device includes a control circuit and a flash memory including a memory array having a plurality of storage blocks. The memory data repair method includes: performing, by the control circuit, a data reading procedure on storage data of the storage blocks; determining, by the control circuit, that one of the storage blocks corresponding to the storage data has a bit inversion error and is an error block according to the data reading procedure; and when a number of the bit inversion errors of the error block is greater than a preset error threshold, performing a memory data repair procedure to control the flash memory to write correction data generated by the data reading procedure on the storage data to the error block.

The application discloses a data refreshing method and an electronic device, and relates to the technical field of storage. Inversion of bits of data stored in a NAND flash memory causes threshold voltage drift, and the threshold voltage drift is closely related to charge leakage, especially the amount of charge leakage. The amount of charge leakage is related to time and temperature, so a mapping table of temperature and retention time can be established in advance in the application. In the case of writing target data into a NAND flash memory, the temperature of the NAND flash memory is monitored to obtain a temperature sequence. Then, mapping parameters of different temperatures in the temperature sequence are queried from the mapping table of temperature and retention time, and the retention time of the target data is determined by using the mapping parameters. In this way, the storage time of the target data and the retention time can be used to determine the remaining retention time. Finally, the target data is refreshed when the remaining retention time is lower than an update threshold. The application has the technical effect of guaranteeing that data is not lost and ensuring reliability.