67 results about "Bit inversion" patented technology

The invention provides a number-theory transformation acceleration method based on sparse data features, and belongs to the field of accelerator system design in privacy calculation. According to the method, the number of times of multiply-add calculation in the butterfly network is reduced by utilizing the sparsity of input data in number theory transformation, and the whole process comprises four steps of bit inversion, pre-calculation, optimization calculation execution and subsequent butterfly network calculation execution. According to the data distribution type after bit inversion in the number-theory transformation, a corresponding optimization calculation method is designed, the preceding-stage calculation data flow of the butterfly network is optimized, multi-stage calculation is combined, unnecessary calculation is avoided, the multiplication and addition times needed in the number-theory transformation are greatly reduced, calculation delay is reduced, and the overall energy efficiency of privacy reasoning is improved; wide application prospects are realized.

The invention discloses a wide-temperature working mode screening method for flash memory particles of a TLC NAND FLASH. The screening method comprises the following steps: S01, executing a card opening test on the flash memory particles; corresponding BLOCK erasing time and writing time in particles are determined, test data stored in an NAND FLASH are read, the number of bit inversion errors is determined, SLC and TLC performance of the BLOCK is tested under various conditions based on test factors such as the erasing time and the number of the bit inversion errors, judgment is carried out, meanwhile, a CLOSE BLOCK test is carried out on the BLOCK in a TLC test mode, and therefore the BLOCK test accuracy is improved. Particle testing and boundary determination conforming to wide-temperature operation are carried out through comprehensive summarization of performance under the condition that BLOCK is only fully written by 1 / 2, the problem that in the prior art, storage screening of a wide-temperature flash memory is poor in reliability is solved, meanwhile, performance of NAND FLASH TLC Client particles is predicted according to a wide-temperature screening strategy and method, and the performance of the NAND FLASH TLC Client particles is predicted according to the wide-temperature screening strategy and method. NAND FLASH particles with potential high-quality performance of high and low temperature work in the future are selected, so that the requirements of higher and stricter application scenes are met.

A system includes a series of first / second transceivers mutually coupled over data lanes as bidirectional transceivers, and first / second control logic coupled to the first / second transceivers, respectively. An encoding of bit inversions by the first / second control logic causes: first pair of transceivers coupled over a first data lane to transmit non-inverted bits in a first direction and a second direction over the first data lane; second pair of transceivers coupled over a second data lane to transmit inverted bits in a first direction but not a second direction over the second data lane; third pair of transceivers coupled over a third data lane to transmit inverted bits in the second direction but not the first direction over the third data lane; and fourth pair of transceivers coupled over a fourth data lane to transmit inverted bits in the first direction and the second direction over the fourth data lane.

Devices, systems, and methods for improving performance of a non-volatile memory are described. An example method includes generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory, and then generating a circular shift flip sequence based on the inversion seed and a flip sequence. The method further includes performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence, processing the intermediate bit sequence to generate an output bit sequence, and finally, writing the output bit sequence to a page in the non-volatile memory. In this example, the page that the output bit sequence is written (or programmed) to is of the page type for which the inversion seed and circular shift flip sequence are generated.

To accurately determine the presence or absence of a memory failure.SOLUTION: In a data processing apparatus 11, respective buffer memories BM of a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2 store therein data formed of a plurality of bits. A CPU 11A reads data from a buffer memory BM, inverts a plurality of bits to generate bit-inverted data resulting from inverting respective values of the plurality of bits, writes the bit-inverted data to the buffer memory BM at a first time, reads the bit-inverted data from the buffer memory BM at a second time later than the first time, and determines the presence or absence of a failure of the buffer memory BM by comparing first data being the bit-inverted data written in the buffer memory BM at the first time with second data being the bit-inverted data read from the buffer memory BM at the second time.SELECTED DRAWING: Figure 1

The invention relates to the field of integrated circuit design, and discloses a processor preamble and mantissa continuous bit parallel counting device and method. The device comprises a 32-bit bit sequence flipping module, a 32-bit bit negation module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module and a 32-bit result output module. According to the invention, parallel counting can be carried out on leading zeros, leading 1, mantissa zeros or mantissa 1 of various data with different precisions in a single processor clock period, so that the required time sequence path length is greatly shortened, the higher processor clock frequency is realized, the multiplexing of a hardware circuit is realized, and the cost is reduced. The circuit greatly reduces the use of transistor resources, reduces the area of a chip, reduces the cost and power consumption of the chip, improves the operation efficiency, universality and adaptability of the processor, and is suitable for being applied to application scenes such as a high-performance digital signal processor and a CPU (Central Processing Unit).

Disclosed is a firmware refreshing method for a storage device, wherein the storage device has been configured with a firmware refreshing mechanism. The firmware refreshing method for the storage device comprises: when a detection time is met, performing bitflip detection on the storage device, and determining the number of bitflips; and if the number of bitflips meets a critical value of redundancy detection, performing firmware refreshing on the storage device according to the firmware refreshing mechanism.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

Disclosed are a data inversion encoding circuit, an eFLASH memory device and an operation method thereof. The data inversion encoding circuit includes a count and comparison circuit, receiving data with plural bits, counting numbers of 0 and 1 in the bits, and outputting a selection signal when number of 0 is larger than number of 1; an inverter, receiving the data and outputting bit inversion data; and a selection circuit, receiving the data and the bit inversion data, and selecting the data or the bit inversion data based on the selection signal. The bit inversion data is output when number of 0 is larger than number of 1.

The application discloses a hardware accelerator and an acceleration method based on a full homomorphic encryption isomorphism mapping, and the accelerator comprises a polynomial storage area, a Tag and Sel reloading unit, a read address calculation unit, a permutation network and a cache unit. The method comprises the following steps: according to the architecture parallelism configured during compilation and the maximum polynomial degree to be supported, after compilation, the isomorphism mapping of the polynomial can be completed according to the actual polynomial degree and the isomorphism parameter of the input. The embodiment of the application can reduce the domain conversion overhead and the overhead of the bit inversion arrangement coefficient, and reduce the calculation burden of the homomorphic rotation. The application can be widely applied to the field of homomorphic encryption technology.

An embodiment of the present application provides a bit operation instruction calculation circuit, chip, processor and electronic device. The bit operation instruction calculation circuit includes a bit reversal module, which is used to arrange the source operands in the instruction to be calculated of the first instruction type in reverse order to obtain an intermediate operand; or, use the source operands in the instruction to be calculated of the second instruction type as the intermediate operand; wherein the first instruction type is used to perform calculations based on the valid bit with the highest bit weight in the source operand, and the second instruction type is used to perform calculations based on the valid bit with the lowest bit weight in the source operand; the calculation module is used to calculate the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determine the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result. This solution reduces the occupied area of the chip.

The invention discloses a data refreshing method and electronic equipment, relates to the technical field of storage, and aims to solve the problem that bit inversion of stored data in a non-flash memory causes threshold voltage drift, and the threshold voltage drift is closely related to charge leakage, in particular to the charge leakage amount. The charge leakage amount is related to the time and the temperature, so that a mapping table of the temperature and the retention time can be established in advance. And under the condition that the target data is written into the NAND flash memory, performing temperature monitoring on the NAND flash memory to obtain a temperature sequence. And then, querying mapping parameters of different temperatures in the temperature sequence from a mapping table of the temperatures and the retention time, and determining the retention time of the target data by utilizing the plurality of mapping parameters. Therefore, the remaining retention time can be determined by using the retention time and the storage timing of the target data. And finally, refreshing the target data under the condition that the remaining retention time is lower than the updating threshold value. The method has the technical effects that the data can be prevented from being lost, and the reliability is ensured.

The application discloses a spectrum extraction method and device of fast Fourier transform, and a computer storage medium, and the method comprises the following steps: adopting inverse sequence output calculation for a front-stage FFT operation, performing linear spectrum processing and logarithmic amplitude operation on a calculation result to obtain an amplitude frequency point; grouping the amplitude frequency point to obtain an amplitude grouping matrix of a preset grouping number; adopting a radix-2 butterfly operation structure to adjust a road number of the amplitude grouping matrix, and storing the amplitude grouping matrix in a sequence after the road number adjustment; dividing the stored amplitude grouping matrix to obtain an amplitude frequency point matrix; marking the position of an element in the amplitude frequency point matrix, performing a binary bit inversion operation on the marked position to obtain a rearranged position; adjusting the position sequence of the element according to the rearranged position to obtain an amplitude frequency point rearranged matrix, and obtaining a spectrum after completing spectrum sequence arrangement and FFTShift operation through serial-parallel conversion. The method realizes parallel sequence arrangement operation of large-point-number spectrum data.

An example system includes logic circuitry to receive digital signals and perform transform operations to generate N output samples for each of the digital signals, k output samples at a time, where k is an integer of 2 or greater and N is an integer multiple of k. Such system further includes circular shift circuitry that includes data multiplexers and address multiplexers to write respective sets of k output samples of the N output samples to k banks of a first memory. For each set of k output samples, the address multiplexers are used to generate k addresses that are bit-reversed with respect to the k output samples, and write a respective one of the k output samples at an indexed ordered position in a respective one of the k banks. The output samples are then read in linear address order from the k banks of the first memory and stored in transposed format in a second memory.

The application discloses a data processing system, method, electronic equipment and storage medium, and relates to the technical field of computers. The original input data is preprocessed into multiple groups of target input data through a data input module, and is input into multiple iteration calculation units to obtain to-be-calculated data and an encoding identifier. When the encoding identifier indicates that the to-be-calculated data needs to be pre-inverted, the to-be-calculated data is pre-inverted to obtain to-be-calculated inverted data. The subsequent iteration calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result. That is, the iteration calculation unit only needs to perform a small amount of data bit inversion on the to-be-calculated inverted data through target calculation to obtain the data processing result. The number of times of data bit inversion in target calculation is reduced, dynamic inversion power consumption is reduced, and, compared with the power consumption reduction mode in the related art, the application does not need high-difficulty chip back-end layout and wiring, and can guarantee the performance and power consumption reduction effect of the chip.

The present invention relates to a data processing device, a memory failure determination method, and a recording medium that accurately determine the presence or absence of a memory failure. In a data processing device (11), each of a first buffer memory (RM1), a second buffer memory (MM1), a third buffer memory (RM2), and a fourth buffer memory (MM2) stores data formed by a plurality of bits, a CPU (11A) reads data from the buffer memory (BM), performs bit inversion for the plurality of bits, generates bit-inverted data after value inversion for each of the plurality of bits, and performs bit inversion for each of the plurality of bits. Bit-inverted data is written to the buffer memory (BM) at a first time, the bit-inverted data is read from the buffer memory (BM) at a second time after the first time, and first data, which is the bit-inverted data written to the buffer memory (BM) at the first time, and second data, which is the bit-inverted data read from the buffer memory (BM) at the second time, are compared. Thus, the presence or absence of a failure in the buffer memory (BM) is determined.

Techniques for number theoretic transform (NTT) and inverse number theoretic transform (iNTT) are described. In some examples, an NTT circuit is to use a decimation-in-frequency (DIF) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order. In some examples, an iNTT circuit is to use a decimation-in-time (DIT) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order.

The present invention relates to a sampling apparatus and method robust against side-channel attacks, the method comprising the steps of: (a) receiving a random bit; (b) setting an iteration loop index i to 0 and determining whether the random bit is greater than or equal to NRCDT[i]; (c) if the random bit is greater than or equal to NRCDT[i], an adjustment value in an i-th iteration loop is set to 1, and if the random bit is smaller than NRCDT[i], the adjustment value in the iteration loop is set to 0; (d) updating a random integer by subtracting the adjustment value from 18; and (e) repeating steps (b) to (d) while increasing i by 1 until i reaches 17, thereby obtaining a finally updated random integer, wherein NRCDT[i] has a value obtained by bit-inverting RCDT[i] of a base sampler.

A method for operating a wireless power transfer system is configured for utilizing software for the purposes of thermal mitigation, via re-encoding data in a bitstream for data communicated in-band of wireless power transfer. The data is encoded as binary messages and, during a message of the bit stream, if the number of high pulses is greater than the number of low pulses, then the message is inverted, such that each of the high pulses of the message invert to a low pulse and each of the low pulses of the message invert to a high pulse. Thus, the data signals will always have 50% or less low pulses in the bit stream.

The application discloses an LDPC decoder and a method and device for early termination of decoding of the LDPC decoder and a medium, and relates to the technical field of LDPC code decoding. The method comprises the following steps: performing multiple decoding iteration processes on to-be-decoded data, and obtaining a corresponding error code word at the end of each decoding iteration process; calculating the to-be-decoded data and the error code word based on a preset bit inversion number calculation formula to obtain a bit inversion number at the end of each decoding iteration process; when a first discriminant weight value obtained at the end of the first decoding iteration process is located in a preset transition interval and the third decoding iteration process ends, obtaining an original error bit number estimation value by estimation according to the first bit inversion number, the second bit inversion number and the third bit inversion number; and when the original error bit number estimation value is greater than a preset threshold, early termination of decoding is performed. The early termination of decoding strategy can be optimized based on the original error bit number estimation value, and the early termination of decoding can be more flexibly and efficiently realized.

The invention relates to the field of data storage, and provides an FPGA program double-area backup method, device and equipment based on SPI FLASH and a medium. The method comprises the following steps: configuring a constraint file of an FPGA project, and generating a backup program bit stream file; a bootstrap program file is constructed, and the bootstrap program file is used for achieving address skipping in the loading process, so that the program skips to the initial position of the overtime loading program; constructing a loading timeout program file, wherein the loading timeout program file comprises timing logic and rollback triggering logic; integrating the boot program file, the backup program bit stream file and the loading timeout program file according to the storage address to obtain an integrated program file; and solidifying the integrated program file into an SPI FLASH, and establishing a double-region backup storage structure. According to the method, the problem that the system cannot be started due to bit reversal errors in long-term storage of the FPGA program is solved, and automatic switching and loading of the backup program are realized.

A system includes a series of first / second transceivers mutually coupled over data lanes as bidirectional transceivers, and first / second control logic coupled to the first / second transceivers, respectively. An encoding of bit inversions by the first / second control logic causes: first pair of transceivers coupled over a first data lane to transmit non-inverted bits in a first direction and a second direction over the first data lane; second pair of transceivers coupled over a second data lane to transmit inverted bits in a first direction but not a second direction over the second data lane; third pair of transceivers coupled over a third data lane to transmit inverted bits in the second direction but not the first direction over the third data lane; and fourth pair of transceivers coupled over a fourth data lane to transmit inverted bits in the first direction and the second direction over the fourth data lane.

The invention discloses a monitoring system based on an APB bus protocol, and solves the problems that in the prior art, only transmission termination and interruption report are supported, the hierarchical error processing capability is lacked, and the detailed context of an overtime event cannot be provided, so that troubleshooting is difficult. The monitoring system comprises a state monitoring unit used for tracking a bus transmission stage through a five-state machine; the dynamic CRC check engine unit is used for supporting 16 / 32-bit configurable polynomial and input and output bit inversion to obtain an updated CRC value and realize single-cycle byte processing; the multi-stage error early warning unit is used for identifying abnormal data in the slave equipment according to the updated CRC value and locking a fault address corresponding to the abnormal data; according to the monitoring system, complete unvarnished transmission of APB signals is achieved through the monitoring system of an APB bus protocol, and real-time monitoring and reliability guarantee of bus affairs are mainly achieved.

The application discloses an operation device and method based on non-0 starting non-cavity coding. By mapping all-0 coding to a non-zero reference value, using a negative number of inverse code, a full-field coding system without negative zero redundancy and coding cavity is constructed, and the bit-by-bit inversion and carry injection operations required by the traditional complement code are completely eliminated. Full-field coding can realize addition and subtraction operations only by switching the reference mirror image, and addition and subtraction have isomorphism, and the efficiency of multiplication and division operations is close, so that the iteration delay of division is significantly reduced. The application has the advantages of small hardware overhead, high operation efficiency, strong compatibility and expansibility, and is suitable for high-performance operation scenes such as CPU, GPU, AI accelerator, DSP and embedded processor.

A balun circuit addresses the bandwidth issue by using symmetric amplitude division and phase delay networks to convert single-ended signals to differential signals. Because the balun circuit's balance characteristics are guaranteed over a very wide bandwidth, other performance characteristics that can limit the operating bandwidth, such as impedance matching and insertion loss, can be carefully addressed without concern for amplitude and phase balance. A balun circuit splits a single-ended signal into four differential paths through symmetric networks and applies phase inversion by inverting the polarity of each differential path, thereby reducing the complexity, size, and loss of the balun circuit's overall configuration.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

The application discloses a high-speed parallel CRC32 computing device and method based on FPGA. The device comprises a data preprocessing module, which is used for performing byte-by-byte bit inversion processing on input data when a data valid signal is valid; a dynamic bit width control module, which is used for acquiring total data length, recording remaining data length and outputting a valid byte number signal; a parallel CRC computing module, which is used for calling a CRC32 computing module with a corresponding bit width according to the valid byte number signal, performing parallel operation on the inverted data and outputting a CRC intermediate result; a result post-processing module, which is used for performing bit inversion and XOR processing on the intermediate result to generate a final check result; and a timing alignment module, which is used for controlling the output timing of a result valid signal through an internal delay counter. The application realizes high-speed parallel checking of any frame length and significantly reduces hardware resource occupation.

According to an example aspect of the present invention, there is provided encode or decode data using a polar code, wherein a generator matrix of the polar code is comprised of rows of a polar transform matrix GN=BNG2⊗n, where BN ;is an N × N bit-reversal matrix, where N = 2n is a non-negative integer and where G2⊗n is an n-fold Kronecker product of G2≜1011, a set of indices of rows of the polar transform matrix which form the generator matrix being set A.

A processing unit is provided which comprises volatile storage for storing machine learning data in binary representation, and a data processing engine communicatively coupled to the volatile storage. The processing unit is configured to selectively invert the bit values in binary representations of portions of the machine learning data when performing storage operations using the volatile storage. A computer-implemented method, and non-transitory computer-readable storage medium comprising instructions for executing the method are also provided. The method comprises receiving a request to perform a storage operation on the volatile storage using the machine learning data and performing the storage operation, including, selecting a portion of the machine learning data and inverting bit values in a binary representation of the selected portion. A computer-implemented method comprising receiving a request to store machine learning data on volatile storage and storing the machine learning data is also provided. Storing the machine learning data includes operating on at least a portion of the machine learning data to prioritize one of two potential bit values.

In a data processing apparatus 11, a buffer memory BM including a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2, stores therein data that is formed of a plurality of bits, and a CPU 11A reads the data from the buffer memory BM, performs bit inversion on the plurality of bits to generate bit inverted data in which a value of each of the bits is inverted, writes the bit inverted data in the buffer memory BM at a first time, reads the data from the buffer memory BM at a second time that is later than the first time, compares first data that is bit inverted data that is written in the buffer memory BM at the first time and second data that is bit inverted data that is read from the buffer memory BM at the second time, and determines presence of a failure in the buffer memory BM.