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Interleave address generating device and interleave address generating method

An address generation and address technology, applied in the direction of error correction/detection, encoding, electrical components, etc. using interleaving technology, can solve the problems of large memory space and large interleaved address pattern generation

Inactive Publication Date: 2001-12-19
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0022] However, in the conventional interleave address generation method, after developing the interleave address pattern generated in a predetermined unit in the memory, row swap processing and offset address addition are performed, so there is a problem that a large amount of time is required to generate the interleave address pattern. memory space and a lot of processing time

Method used

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  • Interleave address generating device and interleave address generating method
  • Interleave address generating device and interleave address generating method
  • Interleave address generating device and interleave address generating method

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Experimental program
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Embodiment 1

[0051] The interleaving address generating apparatus of Embodiment 1 performs row sorting processing and column sorting processing in parallel.

[0052] FIG. 4 is a block diagram showing the structure of the apparatus for generating interleaved addresses according to Embodiment 1 of the present invention.

[0053] The interleave address generation apparatus 100 shown in FIG. 4 mainly includes a counter control unit 101 , a bit inversion unit 102 , a column conversion unit 103 , a shift register 104 , an adder 105 , and a size comparison unit 106 .

[0054] In addition, the column transformation device 103 includes a memory 110 , a memory 111 , a memory 113 , and an exclusive-OR operator 112 .

[0055] In FIG. 4, the counter control unit 101 assigns the row number i of the two-dimensional array (0≤i2 ) is output to the bit inversion device 102, and the column number j of the two-dimensional array (0≤03 ) are output to the memory 111 .

[0056] For example, the counter control ...

Embodiment 2

[0089] FIG. 7 is a block diagram showing an example of the configuration of the interleave address generating apparatus according to the second embodiment. Here, the same reference numerals as those in FIG. 4 are attached to the same structures as those in FIG. 4 , and detailed descriptions thereof are omitted.

[0090] The interleaving address generating apparatus 150 of FIG. 7 is different from that of FIG. 4 in that it includes a memory cell array 151 and adds offset addresses according to the timing of the output from the memory 113 .

[0091] In FIG. 7, the memory cell array 151 temporarily stores the row number i' output from the bit inversion device 102, and then outputs it to the shift register 104.

[0092] For example, with respect to the output value i' from the bit inversion device 102, the memory cell array 151 is composed of a two-stage memory cell array in order to match the timing of the output from the column conversion device 103 and the output from the shift...

Embodiment 3

[0097] FIG. 8 is a block diagram showing an example of the configuration of the interleave address generating apparatus according to the third embodiment.

[0098] In FIG. 8 , the counter control unit 201 outputs the row number i of the two-dimensional array to the memory 202 , and outputs the column number j of the two-dimensional array to the memory 203 .

[0099] The memory 202 stores N(i) corresponding to the input i, and outputs N(i) corresponding to the i output from the counter control unit 201 to the multiplier 204 .

[0100]The memory 203 stores M(j) corresponding to the input j, and outputs M(j) corresponding to the j output from the counter control unit 201 to the adder 205 .

[0101] The adder 205 adds the multiplication result output from the multiplier 204 to M(j) output from the memory 203 , and outputs the addition result to the size comparison unit 206 .

[0102] The size comparison unit 206 outputs the addition result as the interleaving address when the add...

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Abstract

In the counter control unit 101, the block represented by the matrix two-dimensional array is interleaved, the row number and the column number of the two-dimensional array are incremented, and output as a read address value, and in the bit inverting device 102, the read address value is The address value is used as an input to perform bit inversion. In the column conversion device 103, the address value corresponding to the bit inversion output value and the column number from the counter control unit 101 is output as a column conversion value. In the register 104, the output value of the bit inversion device 102 is shifted and output as an address offset value, and in the adder 105, the address offset value and the column exchange value are added, and in the size comparison unit 106 , compare the added value with the interleave size, and output the data within the interleave size as an address value.

Description

technical field [0001] The present invention relates to an interleave address generation apparatus and an interleave address generation method, and in particular, to an interleave address generation apparatus and an interleave address generation method which are very suitable for a communication terminal apparatus or a base station apparatus. Background technique [0002] Conventionally, as an interleave address generating apparatus and an interleaving address generating method, there are the interleaving address generating apparatus and the interleaving address generating method described in Japanese Patent Laid-Open No. 7-212250. [0003] Currently, the work of world standardization of the third-generation communication system is in progress, among which, a standardization scheme related to interleaving is proposed, and GF interleaving is one of the interleaving methods currently under discussion. [0004] The GF interleaving is where the number of rows is N=2 r , the num...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/27
CPCH03M13/2703H03M13/271H03M13/2735H03M13/2771H03M13/00
Inventor 池田彻哉山中隆太朗
Owner PANASONIC CORP
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