Low power consumption compact digital decimation filter for CMOS image sensor

Abstract

The invention discloses a low power consumption compact digital decimation filter for a CMOS image sensor. The low power consumption compact digital decimation filter comprises a ripple counter, a bit-by-bit inversion module BWI, an adder and a 13-bit register, and an inverter and the bit-by-bit inversion module BWI are arranged in front of the adder, the output data bit width of the ripple counter is 7 bit and is half of the output data bit width of the register; an meanwhile, the register only needs 13 bits to realize a 13-bit dynamic range. In practice, since the output data bit width of the ripple counter is 7 bit and is half of the output data bit width of the register, the number of inverters and selectors is reduced by half compared to the original. Meanwhile, the structure guarantees that the register data will not have the problem of data overflow, so the register only needs 13 bits to realize the 13-bit dynamic range without overflowing the data bit register. The low power consumption compact digital decimation filter disclosed by the invention adopts a special structure of pre-BWI, which greatly reduces the number of filter transistors, reduces the power consumption andreduces the cost.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a low-power compact digital decimation filter applied in a CMOS image sensor. Background technique [0002] In a traditional column-parallel CMOS image sensor, a combination of a Sigma-Delta modulator and a digital decimation filter is used to realize AD conversion of pixels. Due to the large scale of the pixel array, the modulator and decimation filter will be reused on a large scale. Therefore, the optimization of a single decimation filter will bring about a huge increase in power consumption and area of ​​the entire system. On the premise of ensuring speed and power consumption, the present invention optimizes the number of transistors to improve performance. [0003] Such as figure 1 Shown is a traditional second-order digital decimation filter structure, which is essentially formed by cascading two-stage digital integrators. The first-stage digital integrator is a...

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Problems solved by technology

[0004] Improvements are needed as current conventional digital decimation filters are not optimized for transistor count and power consumption

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