Radix-2 fast Fourier transform hardware design method based on an FPGA

Abstract

The invention relates to a radix-2 fast Fourier transform hardware design method based on an FPGA. The method is composed of four levels of similar butterfly-shaped units, a twiddle factor multipliermodule, a positive sequence output module and a control module. A circuit structure and a working mode of each level of butterfly-shaped unit are similar, and only the depths of shift registers in thebutterfly-shaped units decrease progressively in sequence according to a geometric progression mode. Each butterfly unitis used for performing addition and subtraction operation on a real part and animaginary part of input data. An operation result enters a subsequent twiddle factor multiplier unit to realize a function of multiplying data by a twiddle factor, odd stages enter a simple twiddle factor multiplier unit, even stages enter a universal twiddle factor multiplier unit, and the twiddle factor after the fourth-stage operation is 1; and the positive sequence output module rearranges the final data result in a bit inversion mode, so that the final data result is output according to a correct sequence.

Description

technical field [0001] The present invention belongs to the category of VLSI (Very Large Scale Integration, referred to as VLSI) design, and designs a base 2 based on the characteristics of modern FPGA technology. 2 The hardware implementation structure of the fast Fourier transform of the algorithm structure. Background technique [0002] Fast Fourier Transform (FFT), developed from Discrete Fourier Transformation (DFT), has become one of the most important algorithms in signal processing, in the fields of communication, filtering, and digital spectrum analysis. have wide application. In order to meet the real-time requirements of digital signal processing, many algorithms and hardware structures have been proposed to improve the processing speed and reduce the usage of hardware resources. [0003] At present, there are mainly four forms of Good-Thomas algorithm, Winograd algorithm, CORDIC algorithm and Cooley-Tukey algorithm. Among them, the Cooley-Tukey algorithm is th...

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Problems solved by technology

In the butterfly unit, Liang Yu et al. changed the data input sequence and control logic to halve the number of adders [3] , but the out-of-sequence data control is very complicated, which is not conducive to large-point FFT calculations; ZhongG et al. used pointer FIFO as the storage unit in the butterfly unit and embedded a Gray code counter, which increased the stability of large-point calculations [4] , but the resource usage has not decreased

In terms of twiddle factor design, LiJ et al. adopted a complex multiplier based on the CORDIC algorithm to remove redundant factor storage, and used a 3-by-5 ​​multiplier structure to reduce the number of complex multipliers [5] , but the disadvantage is that the number of iterations of the CORDIC algorithm is large, and the operation time is long; Zhang Meng et al. calculated the twiddle factor in advance and stored it in the ROM, and completed the operation of multiplying the twiddle factor through an ordinary multiplier [6] , although the control operation is simple, but the multiplier resources take up a lot; Wang and Liu use time-division multiplex multiplier and adder [7] , which improves the calculation speed, but takes up more hardware resources

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