System and method for long addition and long multiplication in associative memory

Abstract

A method for an associative memory device includes replacing a set of three multi-bit binary numbers P, Q and R, stored in the associative memory device, with two multi-bit binary numbers X and Y, also stored in the associative memory device, wherein a sum of the binary numbers P, Q and R is equal to a sum of the binary numbers X and Y. A system includes an associative memory array having rows and columns and a multi-bit multiplier. Each column of the array stores two multi-bit binary numbers to be multiplied. The multi-bit multiplier multiplies, in parallel, the two multi-bit binary numbers per column by concurrently processing all bits of partial products generated by the multiplier. The multiplier performs the processing without any carry propagation delay when adding all but the last two partial products.

Description

technical field [0001] The present invention relates generally to associative memory devices, and in particular to arithmetic operations in associative memory devices. Background technique [0002] In existing computing devices, dedicated electronic circuits can be used to multiply two binary numbers. In multiplying electronic circuits, digital multipliers can be implemented using various techniques; most of these involve computing a set of partial products and then summing the partial products together. The process is similar to teaching elementary school children how to perform long multiplication of decimal numbers. [0003] At each step of the multiplication process of decimal numbers, the partial product represents the result of the multiplication between the multiplicand and the different digits of the multiplier. As we all know, the rightmost digit represents the "1" of the number (10 0 ), the next digit means "ten" (10 1 ), and so on, the remaining digits represe...

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Problems solved by technology

[0011] It will be appreciated that the concurrent multi-bit adder defined in U.S. Patent Application 15 / 690,301, entitled "CONCURRENT MULTI-BIT ADDER," assigned to the common assignee of the present invention and incorporated herein by reference, can Groups of are operated concurrently to improve the complexity of addition, but may not provide concurrent operations for all bits, and may provide complexity proportional to the number if groups of bits > 1

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