System and method for long addition and long multiplication in associative memory

A technology of associative memory and multiplier, applied in the field of arithmetic operations, can solve the problem of not providing concurrent operations for all bits

Active Publication Date: 2019-09-17
GSI TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] It will be appreciated that the concurrent multi-bit adder defined in U.S. Patent Application 15/690,301, entitled "CONCURRENT MULTI-BIT ADDER," assigned to the common assignee of the present invention and incorporated her

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  • System and method for long addition and long multiplication in associative memory
  • System and method for long addition and long multiplication in associative memory
  • System and method for long addition and long multiplication in associative memory

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Embodiment Construction

[0039] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0040] Applicants have realized that a multipurpose associative memory device can improve the complexity of the overall multiplication process by processing all the bits of the partial product concurrently when they are added in the final step, thereby avoiding Carry propagation delay when adding all partial products except the last two.

[0041] Multipurpose associative memory devices that may be used are described in U.S. Patent No. 8,238,173, issued Aug. 7, 2012, entitled "USING STORAGE CELLS TO PERFORM COMPUTATION"; Patent Publication 2015 / ...

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Abstract

A method for an associative memory device includes replacing a set of three multi-bit binary numbers P, Q and R, stored in the associative memory device, with two multi-bit binary numbers X and Y, also stored in the associative memory device, wherein a sum of the binary numbers P, Q and R is equal to a sum of the binary numbers X and Y. A system includes an associative memory array having rows and columns and a multi-bit multiplier. Each column of the array stores two multi-bit binary numbers to be multiplied. The multi-bit multiplier multiplies, in parallel, the two multi-bit binary numbers per column by concurrently processing all bits of partial products generated by the multiplier. The multiplier performs the processing without any carry propagation delay when adding all but the last two partial products.

Description

technical field [0001] The present invention relates generally to associative memory devices, and in particular to arithmetic operations in associative memory devices. Background technique [0002] In existing computing devices, dedicated electronic circuits can be used to multiply two binary numbers. In multiplying electronic circuits, digital multipliers can be implemented using various techniques; most of these involve computing a set of partial products and then summing the partial products together. The process is similar to teaching elementary school children how to perform long multiplication of decimal numbers. [0003] At each step of the multiplication process of decimal numbers, the partial product represents the result of the multiplication between the multiplicand and the different digits of the multiplier. As we all know, the rightmost digit represents the "1" of the number (10 0 ), the next digit means "ten" (10 1 ), and so on, the remaining digits represe...

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Application Information

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IPC IPC(8): G06F7/501G06F7/523
CPCG06F7/501G06F7/523G06F7/533G06F7/5312G06F7/5318
Inventor M·拉泽
Owner GSI TECH
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