5 results about "Binary addition" patented technology

This invention discloses a binary adder array and method based on node decision, relating to the field of integrated circuits. It aims to solve the problems of high dynamic power consumption, reliance on critical path delay, and complex asynchronous adder circuitry in traditional adders. The method includes: calculating the carry propagation signal Pi and the carry generation signal Gi in parallel using operands A and B; generating a decision node Di for each bit i based on Pi and Gi; setting Di low when Gi=1, setting Di high when Gi=0 and Pi=0, and assigning the state Di-1 to Di when Pi=1; generating the next bit sum signal Si+1 based on Di; outputting ~Pi+1 when Di is low, and outputting Pi+1 when Di is high. Signal transmission is achieved by controlling the on / off state of physical channels, rather than cascading logic gates. The device includes a logic operation module and an output control module. The output control module includes a node control network with level injection units and level transmission switches, all connected to the decision node Di. This invention also provides an asynchronous adder array composed of multiple cascaded adder units and a chip integrating this circuit. This invention achieves conditional signal propagation through a unique decision node network and physical channel control, which can significantly reduce dynamic power consumption when the input data is sparse, and naturally supports asynchronous operation, with the advantages of high energy efficiency and easy expansion.

The embodiment of the invention provides a data processing method and device and electronic equipment. The data processing method comprises the steps of obtaining an information query request sent by a request end; in the database server, at least one target encrypted data matched with the information query request is queried and obtained, the target encrypted data are numerical data, the target encrypted data correspond to slot position information, and the target encrypted data are encrypted through a fully homomorphic encryption algorithm; determining a half-folding coefficient for performing accumulation calculation on the at least one target encrypted data; performing half-and-half addition calculation on the at least one piece of target encrypted data based on a half-and-half coefficient, and determining an encrypted data sum matched with the information query request; and returning the sum of the encrypted data and the quantity information of the at least one piece of target encrypted data to the request end. In the embodiment of the invention, the data query operation is realized through the half-and-half addition algorithm, so that the query time required by the information query operation is effectively saved, and the data query efficiency is improved.

The invention discloses a data storage method applied to a block chain, a data access verification method and equipment, and is applied to the technical field of block chains. Processing the to-be-stored data according to the key information to obtain an encrypted data set and a binary addition tree diagram; and determining adder tree storage proof information based on the binary addition tree diagram, the encrypted data set and the user identification information, and performing uplink storage. The data access verification method comprises the steps that after a data access verification request is received, adder tree storage certification information and historical random path spot check space-time certification information are called; obtaining a second random number, processing the second random number according to the additive tree storage proof information or the historical random path spot check space-time proof information, and generating random path spot check space-time proof information; and the data state information is determined according to the random path spot check space-time proof information, so that data storage and access verification processing are realized, the computing resource consumption is reduced, and the deployment flexibility is improved.

This application provides a data processing method, apparatus, and electronic device. The data processing method includes: obtaining an information query request sent by a requesting end; querying a database server to obtain at least one target encrypted data matching the information query request, wherein the target encrypted data is numerical data, corresponds to slot information, and is encrypted using a fully homomorphic encryption algorithm; determining a binary coefficient for accumulating the at least one target encrypted data; performing binary addition on the at least one target encrypted data based on the binary coefficient to determine the sum of encrypted data matching the information query request; and returning the sum of encrypted data and the quantity information of the at least one target encrypted data to the requesting end. In this application embodiment, the binary addition algorithm is used to implement the data query operation, effectively saving the query time required for the information query operation, thereby improving the data query efficiency.

The present application relates to the field of pulse neural network circuit design, in particular to a configurable multi-head self-attention event calculation architecture of a pulse neural network.The present application introduces a configurable segmentation code arranged between two bits of AER coding on the basis of pulse AER coding, and realizes the segmentation code corresponding to the desired hyperparameter;The configurable segmentation code enables the segmentation vector matrix multiplication processing unit to efficiently and accurately calculate for different Token dimensions d and MHSA head numbers h, thereby realizing the efficient compatibility of the same hardware architecture with various hyperparameter Spiking ViT architecture neural network models.Based on the above configurable segmentation coding scheme, the present application realizes high energy efficiency event calculation, improves circuit reusability, and reduces hardware resource requirements;The event calculation architecture of the present application adopts binary addition operation instead of complex floating point multiplication operation with the aid of the high sparsity characteristics of SNN, and also improves the energy efficiency of the circuit.