ROL quasi-cyclic matrix multiplier for full parallel input in WPAN

Abstract

The invention provides an ROL quasi-cyclic matrix multiplier for full parallel input in a WPAN. The multiplier is used for multiplication of a vector m and a quasi-cyclic matrix F in standard QC-LDPC approximate triangle coding of the WPAN. The multiplier comprises two generating polynomial lookup tables for pre-storing all cyclic matrix cyclic generating polynomials in the matrix F, two 21-bit binary multipliers for performing scalar multiplication on the vector section and generating polynomial bits of the m, 21 three-bit binary adders for performing modulo-2 adding on content of a product sum shifting register and a 21-bit shifting register for storing the sum subjected to one-bit ROL. The multiplier for full parallel input is suitable for QC-LDPC codes in the WPAN standard and has the advantages of having fewer registers, being small in power consumption, low in cost, high in working frequency and large in throughput capacity, and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a cyclic left-shift quasi-circular matrix multiplier with full parallel input in WPAN standard QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulatory matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit; the first column of the circulatory matrix is ​​the result of the cyclic shift of the last column by 1 bit, and the remaining columns They are all th...

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Problems solved by technology

[0020] The existing solution of the quasi-circular matrix multiplier with full parallel input in the WPAN standard QC-LDPC approximate lower triangular coding has two disadvantages: one is that 42 registers are required, resulting in large power consumption and high cost of the circuit; the other is that the modulo 2 The adder has 42 input terminals, and the delay of the addition operation is long, which will result in low operating frequency and low throughput of the multiplier

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