135 results about "Circulant matrix" patented technology

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.

A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

An automated tuning method of a large-scale multivariable model predictive controller for multiple array papermaking machine cross-directional (CD) processes can significantly improve the performance of the controller over traditional controllers. Paper machine CD processes are large-scale spatially-distributed dynamical systems. Due to these systems' (almost) spatially invariant nature, the closed-loop transfer functions are approximated by transfer matrices with rectangular circulant matrix blocks, whose input and output singular vectors are the Fourier components of dimension equivalent to either number of actuators or number of measurements. This approximation enables the model predictive controller for these systems to be tuned by a numerical search over optimization weights in order to shape the closed-loop transfer functions in the two-dimensional frequency domain for performance and robustness. A novel scaling method is used for scaling the inputs and outputs of the multivariable system in the spatial frequency domain.

The invention discloses an algebraic construction method of LDPC (Low Density Parity Check) code based on cyclic matrixes; design parameters of cyclic matrixes are adjusted by short-loop check and minimum code weight check, which are nonnegative prime numbers a and b meeting two constraint conditions, and dimension q of an identity matrix, wherein the magnitude of dimension q of a shift identity matrix and whether the error rate characteristics of the designed LDPC code are influenced by prime numbers. The invention solves the problems of short-loop and low code coincident code word appearing in the existing QC LDPC code design. The method can check the existence of low code coincident code word in the designed code, thereby checking the existence of 4-loop. An irregular quasi-cyclic LDPC code structure disclosed by the invention divides the check matrix H into two submatrixes A and B, the nonsingular structure of the submatrix A is disclosed, and a matrix is generated by the two submatrixes A and B. Direct linear coding is carried out by generating the matrix. The embodiment validates the efficiency and good bit rate performance of the method disclosed by the invention.

The invention provides a quasi-cyclic LDPC serial encoder based on ring shift left, which includes c generator polynomial lookup tables of all cyclic matrix generator polynomials in a prestored generated matrix, c b-bit binary multipliers for performing scalar multiplication to information bit and generator polynomials, c b-bit binary adders for performing modulo-2 adding to product and content of shifting registers, and c b-bit shifting registers for storing the sum of ring shift left for 1 bit, and finally, the checking data is stored in the c shifting registers. The serial encoder provided by the invention has the advantages of few registers, simple structure, low power consumption, low cost and the like.

A transmitter may map, using a selected modulation constellation, each of C′ bit sequences to a respective one of C′ symbols, where C′ is a number greater than one. The transmitter may process the C′ symbols to generate C′ inter-carrier correlated virtual subcarrier values. The transmitter may decimate the C′ virtual subcarrier values down to C physical subcarrier values, C being a number less than C′. The transmitter may transmit the C physical subcarrier values on C orthogonal frequency division multiplexed (OFDM) subcarriers. The modulation constellation may be an N-QAM constellation, where N is an integer. The processing may comprise filtering the C′ symbols using an array of C′ filter tap coefficients. The filtering may comprise cyclic filtering. The filtering may comprise multiplication by a circulant matrix populated with the C′ filter tap coefficients.

The invention provides a quasi-cyclic matrix serial multiplier based on rotate left. The quasi-cyclic matrix serial multiplier is used for implementing multiplication of a vector m and a quasi-cyclic matrix F in QC-LDPC (quasi-cyclic low-density parity-check) approximate lower triangular encodings. The multiplier comprises u generated polynomial lookup tables, u b-bit binary multipliers, u b-bit binary summators and u b-bit shift registers. The generated polynomial lookup tables are used for pre-storing quasi-cyclic matrix generated polynomial in the matrix F. The b-bit binary multipliers are used for performing scalar multiplication of the vector m data bit and the generated polynomial. The b-bit binary summators are used for performing modulo-2 adding of products and shift register contents. The b-bit shift registers are used for storing sums of 1-bit movements subjected to rotate left. The quasi-cyclic matrix serial multiplier has the advantages of small number of registers, simple structure, low power consumption and cost and the like.

The invention discloses an LDPC code constructing method based on coding cooperative communication; the method comprises the following steps: 1. choose a basis matrix W (1) based on finite field multiplicative inverse; the multiplicative inverse of a certain element in the basis matrix is multiplied with each row of the basis matrix, so as to generate a multiplicative identity in the basis matrix; 3.the basis matrix is expanded, so as to obtain an expansion matrix containing diagonal line; 4. the submatrix above the diagonal line is substituted by zero matrix, so as to obtain a quasi-cyclic matrix which is provided with a lower triangular type and has a nested structure; the invention can flexibly construct the quasi-cyclic matrix with the nested structure, which is suitable for CC proposal, while reducing the code construction complexity, the complexity of a coder of a trunk node and a destination node is reduced; in addition, the code in the invention does not have short link characteristic, and the performance of the code is promoted obviously compared with the traditional decode and forward, DF proposal.

An irregular parity check matrix is generated which has an LDGM structure in which a masking quasi-cyclic matrix and a matrix in which cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location. A mask matrix capable of supporting a single encoding rate for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. The irregular parity check matrix is masked using a generated mask matrix, and a parity check matrix is generated combining a masked irregular parity check matrix with a lower triangular matrix formed in a staircase manner to satisfy a single encoding rate.

A check matrix creation device includes a circulant permutation matrix setting unit 12 for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger, and a quasi-cyclic matrix creation unit 13 for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in a row direction and in a column direction to create a quasi-cyclic matrix.

The invention provides a rotate left-based quasi-cyclic (QC) matrix serial multiplier in deep space communication, which is used for realizing the multiplication of a vector m and a quasi-cyclic matrix F in triangle coding under standard multi-code class QC-LDPC approximate in the deep space communication of consultative committee for space data systems (CCSDS). The multiplier comprises 4 generating polynomial lookup tables which prestore cyclic matrix generating polynomials of all code class matrixes F, 4 2048-bit binary multipliers which perform scalar multiplication on the data bit of the vector m and the generating polynomials, 4 2048-bit binary adders which perform modulo 2 addition on products and contents of shift registers, and 4 2048-bit shift registers which store the sums which are rotated left for one bit. The quasi-cyclic matrix serial multiplier provided by the invention is compatible with all code classes, and has the advantages of few registers, simple structure, low power consumption, low cost and the like.

A regular quasi-cyclic matrix is generated in which specific regularity is given to cyclic permutation matrices. A mask matrix capable of supporting a plurality of encoding rates is generated. A specific cyclic permutation matrix in the regular quasi-cyclic matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix with an LDGM structure is generated in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

The invention provides an ROL quasi-cyclic matrix multiplier for full parallel input in a WPAN. The multiplier is used for multiplication of a vector m and a quasi-cyclic matrix F in standard QC-LDPC approximate triangle coding of the WPAN. The multiplier comprises two generating polynomial lookup tables for pre-storing all cyclic matrix cyclic generating polynomials in the matrix F, two 21-bit binary multipliers for performing scalar multiplication on the vector section and generating polynomial bits of the m, 21 three-bit binary adders for performing modulo-2 adding on content of a product sum shifting register and a 21-bit shifting register for storing the sum subjected to one-bit ROL. The multiplier for full parallel input is suitable for QC-LDPC codes in the WPAN standard and has the advantages of having fewer registers, being small in power consumption, low in cost, high in working frequency and large in throughput capacity, and the like.

A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

The invention is applicable in the technical field of encoding, and provides a method and a device for encoding an LDPC code. The encoding device comprises a storage unit which is used for storing encoding information source information, a check encoding calculation unit which is used for calculating the encoding information source information of a register according the a check matrix with a Toeplitz structure and an exclusive OR unit which is used for outputting a calculated result after exclusive OR, wherein the check code unit is provided with the check matrix with the Toeplitz structure.The device and the method partition the check matrix, and encode the received information source information according to partitioned check matrix, wherein the partitioned check matrix is provided with the Toeplitz structure. In the embodiment of the invention, values of converse diagonal lines of the matrix are completely the same, contribute to adopt operation in a production line mode, and have excellent regularity; and a sparse quasi-cyclic matrix structure brings great convenience to encoding and saves hardware resources.

A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor are disclosed herein. The parity-check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix having the entries circular shifted row-by-row. The double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row. The processing module is configured to process an input signal and output an output signal correspond to the parity-check matrix of a low density parity check code (LDPC).

The invention discloses a multi-mechanism mixed recurrent neural network model compression method. The multi-mechanism mixed recurrent neural network model compression method comprises A, carrying outcirculant matrix restriction: restricting a part of parameter matrixes in the recurrent neural network into circulant matrixes, and updating a backward gradient propagation algorithm to enable the network to carry out batch training of the circulant matrixes, B, carrying out forward activation function approximation: replacing a non-linear activation function with a hardware-friendly linear function during the forward operation process, and keeping the backward gradient updating process unchanged; C, carrying out hybrid quantization: employing different quantification mechanisms for differentparameters according to the error tolerance difference between different parameters in the recurrent neural network; and D, employing a secondary training mechanism: dividing network model training into two phases including initial training and repeated training. Each phase places particular emphasis on a different model compression method, interaction between different model compression methodsis well avoided, and precision loss brought by the model compression method is reduced to the maximum extent. According to the invention, a plurality of model compression mechanisms are employed to compress the recurrent neural network model, model parameters can be greatly reduced, and the multi-mechanism mixed recurrent neural network model compression method is suitable for a memory-limited andlow-delay embedded system needing to use the recurrent neural network, and has good innovativeness and a good application prospect.