Quasi-cyclic LDPC serial encoder based on ring shift left

Abstract

The invention provides a quasi-cyclic LDPC serial encoder based on ring shift left, which includes c generator polynomial lookup tables of all cyclic matrix generator polynomials in a prestored generated matrix, c b-bit binary multipliers for performing scalar multiplication to information bit and generator polynomials, c b-bit binary adders for performing modulo-2 adding to product and content of shifting registers, and c b-bit shifting registers for storing the sum of ring shift left for 1 bit, and finally, the checking data is stored in the c shifting registers. The serial encoder provided by the invention has the advantages of few registers, simple structure, low power consumption, low cost and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a serial coder of a quasi-cyclic LDPC code in a communication system. Background technique [0002] Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of cyclic matrices, which have the characteristics of segmental circulation, so they are called quasi-cyclic LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The communication system usually adopts the QC...

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Problems solved by technology

[0012] The existing implementation scheme of QC-LDPC serial encoding in the communication system has the disadvantages of large power c

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