Quasi-cyclic matrix serial multiplier based on rotate left

A technology of quasi-circular matrix and cyclic left shift, which is applied in the field of channel coding, can solve the problems of high cost, large circuit power consumption, and a large number of registers, and achieve the effect of simple structure, reduced power consumption, and reduced registers

Inactive Publication Date: 2013-08-28
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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Problems solved by technology

[0020] The existing solution of quasi-circular matrix serial multiplication in QC-LDPC approximate lower triangular coding is based on u SRAA-I circuits. One of the disadvantages of this scheme is that a large number of registers are required, which will inevitably result in high power consumption and high cost of the circuit.

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  • Quasi-cyclic matrix serial multiplier based on rotate left
  • Quasi-cyclic matrix serial multiplier based on rotate left
  • Quasi-cyclic matrix serial multiplier based on rotate left

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Embodiment Construction

[0029] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0030] Since the generator polynomial f of the circulant matrix i,j Rotating right n bits is equivalent to rotating it left b-n bits, ie f i , j r ( n ) = f i , j l ( b - n ) , Then equation (8) can be rewritten as

[0031] ...

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Abstract

The invention provides a quasi-cyclic matrix serial multiplier based on rotate left. The quasi-cyclic matrix serial multiplier is used for implementing multiplication of a vector m and a quasi-cyclic matrix F in QC-LDPC (quasi-cyclic low-density parity-check) approximate lower triangular encodings. The multiplier comprises u generated polynomial lookup tables, u b-bit binary multipliers, u b-bit binary summators and u b-bit shift registers. The generated polynomial lookup tables are used for pre-storing quasi-cyclic matrix generated polynomial in the matrix F. The b-bit binary multipliers are used for performing scalar multiplication of the vector m data bit and the generated polynomial. The b-bit binary summators are used for performing modulo-2 adding of products and shift register contents. The b-bit shift registers are used for storing sums of 1-bit movements subjected to rotate left. The quasi-cyclic matrix serial multiplier has the advantages of small number of registers, simple structure, low power consumption and cost and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a quasi-circular matrix serial multiplier in QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and QC-LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] When using the approximate lower triangular enc...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/525
Inventor 张鹏刘志文张燕
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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