Quasi cyclic matrix serial multiplier free of multiplication

Abstract

The invention provides a quasi cyclic matrix serial multiplier free of multiplication. The quasi cyclic matrix serial multiplier free of the multiplication is used for realizing multiplication of a vector m and a quasi cyclic matrix F in QC-LDPC approximate lower triangular codes. The multiplier comprises u cyclic matrix generator polynomials pre-stored in a matrix F, a generator polynomial lookup table of a b-position null vector, u b-position binary adders outputting the generator polynomial lookup table and conducting analog 2 adding on contents of a shifting register, and u b-position shifting registers for storing results of cyclic shift left one position. The quasi cyclic matrix serial multiplier removes the multiplication, and has the advantages of being few in logic resource, simple in structure, low in consumption, low in cost, and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a quasi-circular matrix serial multiplier in QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of the efficient channel coding techniques, and QC-LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] When using the approx...

AI Technical Summary

Problems solved by technology

[0020] The existing solution for quasi-circular matrix serial multiplication in QC-LDPC approximate lower triangular coding is based on u SRAA-I circuits. The disadvantage of this scheme is that the number of registers is large, and a large number of AND gates are required to complete the multiplication operation, so many logic resources It is bound to cause large power consumption and high cost of the circuit

Images