5results about How to "Save logic resources" patented technology

This invention belongs to the field of digital control systems for power electronic devices. It provides a high-speed communication system and method for multiple units of CHB frequency converter based on FPGA ping-pong buffer. By building an efficient parallel processing architecture at the FPGA hardware level, it realizes zero-wait instruction issuance and instantaneous status acquisition between the controller and dozens of distributed power units, compressing the system communication and processing time from milliseconds to hundreds of microseconds, achieving the technical effect of CHB frequency converters achieving extremely short control cycles and high dynamic performance.

The application relates to a request management device and method, a DPU, a storage medium, and a program product. The device comprises a management unit, which comprises a memory, a row bitmap register, a row scheduler, a data bitmap register, and a control module. The plurality of bits of the memory correspond to virtual queues one by one and are arranged in rows and columns. The value of each bit is used to indicate whether a to-be-scheduled request is cached. The row bitmap register is used to indicate whether each row has a to-be-scheduled request. The row scheduler is used to select a target row from the rows having to-be-scheduled requests. The data bitmap register is used to cache all bit data of the target row. The column scheduler is used to select a target column from the data bitmap register. The control module is used to receive a to-be-scheduled request, set the corresponding position in the memory to 1 according to the virtual queue number in the to-be-scheduled request, calculate a target virtual queue according to the target row selected by the row scheduler and the target column selected by the column scheduler, and output a target to-be-scheduled request. The application can reduce resource consumption and automatically merge repeated requests.

This invention discloses an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, comprising the following steps: S1, buffering the input one-dimensional signed number sequence x(n) into five points and outputting the data in two's complement form in parallel according to a specific timing sequence; S2, preprocessing the parallel data output in S1; S3, performing parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between the data, and storing the comparison results in the corresponding size relationship registers; S4, calculating the redundancy output median index number based on the preprocessed parallel data in S2 and the value of the size relationship register in S3; S5, using the median index number calculated in S4, selecting the index value of the corresponding index number in the original parallel data for output using a MUX. This method outputs the median filtering result with fewer comparisons, less clock delay, less hardware logic resources, and lower computational latency.

The application discloses a pulse width modulation frequency and working period calculation method and a fan control system. The calculation method comprises the following steps: receiving a rotating speed information; converting the rotating speed information into a first two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of M to generate a second two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of P to generate a third two-digit rotating speed information; adding the second two-digit rotating speed information and the third two-digit rotating speed information to generate a fourth two-digit rotating speed information; and generating a rotating speed count signal according to a first system clock frequency and a working period intermediate value by using a counter.

The application discloses a kind of sensor signal active fault-tolerant control system for strong electromagnetic pulse environment, belong to digital control fault-tolerant technical field.System includes the pre-processing module, signal identification module, pseudo-cluster separation module and signal reconstruction module connected in turn.Pretreatment module carries out FIR low-pass filtering to original sensor signal;Signal identification module generates abnormal flag by sliding window difference and energy mutation monitoring;Pseudo-cluster separation module carries out pseudo-cluster to continuous abnormal flag by finite state machine, and outputs interference section mask;Signal reconstruction module reconstructs signal to interference section based on mask, using local autoregressive prediction model.The scheme can identify and reconstruct sensor signal distorted due to strong electromagnetic pulse interference in real time and efficiently, significantly improve the reliability and robustness of digital control system such as aero-engine in complex electromagnetic environment, and is particularly suitable for FPGA platform implementation.