15results about How to "Save logic resources" patented technology

The invention discloses an echo segmented pulse compression method under a high sampling rate based on an FPGA (Field Programmable Gate Array). According to the method, down-sampling preprocessing is firstly carried out on the signals sampled by the ADC with the sampling rate of 124 MHz, the sampling rate is reduced to 62 MHz on the premise that spectrum aliasing does not happen to the signals, then segmentation range pulse compression is carried out on the 1PRT echo signals, the total processing amount is reduced by 40%, the data calculation amount can be remarkably reduced, the operation speed and the data processing efficiency can be improved, and the method is suitable for large-scale popularization and application. And FPGA logic resources are saved. And short-time 1s echo pulse compression preprocessing is realized by adopting a method of synthesizing 1000 PRTs, so that the communication data rate is greatly reduced. And in cooperation with operation of other components of the surface scene deformation monitoring system, the system reliability is improved, and the scene deformation monitoring task can be smoothly carried out.

The invention relates to a shared bus type distributed MBIST system, and belongs to the technical field of MBIST architecture. According to the shared bus type distributed MBIST architecture, a Memory Interface module in a Tesent MBIST architecture is removed, an MBIST controller is reserved, and a shared bus controller is additionally arranged in the MBIST controller, so that a data path and a control path are built between the MBIST controller and Memory, and the data path and the control path comprise an address bus, a data bus, a read-write enable, a chip selection enable and other control buses which can be reused and are used for accessing the Memory. According to the shared bus type distributed MBIST architecture, a Memory Interface module is not needed, the problems that the chip area and power consumption are large due to the fact that multiple Memory Interfaces need to be adopted at present are solved, logic resources can be reduced to the maximum extent, the logic complexity can be reduced, and testing of Memory in a chip is achieved.

The invention discloses an FPGA (Field Programmable Gate Array) interface logic resource multiplexing structure and a phased-array antenna beam forming system. The FPGA interface logic resource multiplexing structure comprises a transmitting end module and a receiving end module, the sending end module is used for firstly sending a verification sequence to the receiving end module, calibrating a receiving end, and sending user data to the receiving end module after calibration is completed; the calibration sequence and the user data are multi-bit wide data and are converted into high-speed serial data to be output; and the receiving end module is used for receiving the calibration sequence and the high-speed serial data, performing calibration according to the calibration sequence, and converting the high-speed serial data into low-speed parallel data to be output after the calibration is completed. By utilizing the scheme of the invention, the interface logic resource multiplexing can be flexibly and efficiently realized.

The invention discloses a multi-format compatible space laser communication receiving device and method, belongs to the technical field of free space optical communication, and aims to solve the problems that an existing system is high in complexity and maintenance cost and poor in dynamic channel characteristic applicability in a space laser communication system. The C-band tunable laser is connected with the IQ modulator through an optical fiber, the IQ modulator is connected with the power amplifier, the power amplifier is connected with the transmitting antenna through an optical fiber, the transmitting antenna is in wireless transmission with the receiving antenna, the receiving antenna is connected with the optical fiber coupler through an optical fiber, and the optical fiber coupler is connected with the pre-amplifier and the optical power module through optical fibers. The preamplifier, the photoelectric detector and the analog-to-digital converter are sequentially connected through optical fibers, the analog-to-digital converter is connected with the FPGA through a radio frequency line, and the optical power module and the temperature pulsation instrument are respectively connected with the FPGA through USB data lines. The multi-format compatible receiving and the high rate are met, meanwhile, the requirement for system hardware is lowered, the cost is low, and the reliability is high.

This invention belongs to the field of digital control systems for power electronic devices. It provides a high-speed communication system and method for multiple units of CHB frequency converter based on FPGA ping-pong buffer. By building an efficient parallel processing architecture at the FPGA hardware level, it realizes zero-wait instruction issuance and instantaneous status acquisition between the controller and dozens of distributed power units, compressing the system communication and processing time from milliseconds to hundreds of microseconds, achieving the technical effect of CHB frequency converters achieving extremely short control cycles and high dynamic performance.

The present invention discloses a narrowband multi-subband time division radio frequency remote unit and a sub-band separation and combination method, wherein the narrowband multi-subband time division radio frequency remote unit comprises a multi-channel direct digital frequency synthesizer group, a downlink digital up-converter unit, an uplink digital down-converter unit, a multiplier group for downlink sub-band combination, a multiplier group and an accumulator for uplink sub-band separation. The present invention can save a lot of hardware resources and logic resources in the application scenario of ultra-multi-carrier by multiplexing the direct digital frequency synthesizer group.

The invention belongs to the technical field of image preprocessing, and discloses an image preprocessing method and system based on an FPGA. The method comprises the following steps of: realizing a gray scale transformation function module FPGA (Field Programmable Gate Array), realizing an image denoising function module FPGA, and carrying out noise reduction processing on an image in the FPGA through mean filtering and median filtering; the background superposition and image zooming function module is realized by an FPGA (Field Programmable Gate Array), an Alpha channel is added in the FPGA to control the transparency of a display object, and floating point operation is replaced by magnification times to realize image background superposition; after image background superposition, resolution reduction is carried out on the image, and the image is displayed on a screen. According to the method, an efficient implementation process of combined application of basic image preprocessing algorithms of gray level transformation, denoising, Alpha background superposition and image scaling in the FPGA is realized, and an interface is reserved for realizing a specific image processing algorithm module for subsequent secondary development.

The application relates to a request management device and method, a DPU, a storage medium, and a program product. The device comprises a management unit, which comprises a memory, a row bitmap register, a row scheduler, a data bitmap register, and a control module. The plurality of bits of the memory correspond to virtual queues one by one and are arranged in rows and columns. The value of each bit is used to indicate whether a to-be-scheduled request is cached. The row bitmap register is used to indicate whether each row has a to-be-scheduled request. The row scheduler is used to select a target row from the rows having to-be-scheduled requests. The data bitmap register is used to cache all bit data of the target row. The column scheduler is used to select a target column from the data bitmap register. The control module is used to receive a to-be-scheduled request, set the corresponding position in the memory to 1 according to the virtual queue number in the to-be-scheduled request, calculate a target virtual queue according to the target row selected by the row scheduler and the target column selected by the column scheduler, and output a target to-be-scheduled request. The application can reduce resource consumption and automatically merge repeated requests.

A multi-format compatible space laser communication receiving device and method belongs to the field of free space optical communication technology. In order to solve the problem of high complexity and high maintenance cost of the existing system, and facing the problem of poor applicability of dynamic channel characteristics in the space laser communication system, the signal source of the device is connected to the IQ modulator through a radio frequency line, the C-band tunable laser is connected to the IQ modulator through an optical fiber, the IQ modulator is connected to the power amplifier, the power amplifier is connected to the transmitting antenna through an optical fiber, the transmitting antenna and the receiving antenna are wirelessly transmitted, the receiving antenna is connected to the optical fiber coupler through an optical fiber, the optical fiber coupler is respectively connected to the preamplifier and the optical power module through an optical fiber, the preamplifier, the photodetector, and the analog-to-digital converter are connected in turn through optical fibers, the analog-to-digital converter and the FPGA are connected with an radio frequency line, and the optical power module and the temperature pulsator are respectively connected to the FPGA through a USB data line. While meeting the requirements of multi-format compatible reception and high speed, the requirements for system hardware are reduced, the cost is low and the reliability is high.

The present invention discloses an online cluster reconstruction method, device and equipment of a high counting rate twin-TPC, the method comprising: generating a reference window based on a front-end data packet collected by the twin-TPC, and caching the reference window information and corresponding pulse data to a RAM according to the generated reference window; performing adjacent window merging, reference window shunting and reference window merging processing in the boundary area of ​​adjacent time windows within the data packet; based on each reference window after processing and the corresponding pulse information, using the "first rise and then fall" trend to find the cluster center channel, and screening out the effective pulse information near the cluster center channel; based on the effective pulse information, using the center of gravity method to restore the position information of the incident particles, and realizing online reconstruction of the cluster. The present invention can be widely used in the field of nuclear detection, especially in the future radioactive nuclear beam physics experiments carried out on advanced high-current heavy ion accelerator devices.

The present invention provides a method, system, control method and control system for managing and storing Bmp pictures in a module signal generator of FPGA, the method comprising the following steps: storage adjustment step: filling and storing each pixel in the Bmp picture according to a first set value, and filling and storing the number of pixels in each row of the Bmp picture according to an integer multiple of a second set value, so that the pixel storage size of each row of the Bmp picture is an integer multiple of the FPGA memory interface; calculation step: calculating the starting address of each row of pixels of the Bmp picture stored in the memory. The beneficial effects of the present invention are: the present invention can simultaneously meet different functional requirements such as high-resolution picture refresh bandwidth, movement, split screen, etc. under different resolutions, color depths, and refresh rates; through the present invention, the FPGA logic code is simple to implement and consumes less logic resources.

The invention discloses a control signal monitoring system for an FPGA camera, and the system comprises a signal sampling module which is used for obtaining a plurality of control signals in the camera; the clock frequency division module is used for dividing the frequency of a system clock into a signal sampling clock; the control module is used for sampling the control signal according to a preset condition; the bus module is used for transmitting data; wherein the signal sampling module is electrically connected to the control module, the clock frequency division module is electrically connected to the clock frequency division module, and the signal sampling module, the clock frequency division module and the control module are respectively connected to the bus module. The control signal monitoring system for the FPGA camera has the beneficial effects that the accuracy of debugging parameters is improved by directly acquiring a real control signal in the camera.

This invention discloses an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, comprising the following steps: S1, buffering the input one-dimensional signed number sequence x(n) into five points and outputting the data in two's complement form in parallel according to a specific timing sequence; S2, preprocessing the parallel data output in S1; S3, performing parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between the data, and storing the comparison results in the corresponding size relationship registers; S4, calculating the redundancy output median index number based on the preprocessed parallel data in S2 and the value of the size relationship register in S3; S5, using the median index number calculated in S4, selecting the index value of the corresponding index number in the original parallel data for output using a MUX. This method outputs the median filtering result with fewer comparisons, less clock delay, less hardware logic resources, and lower computational latency.

The application discloses a pulse width modulation frequency and working period calculation method and a fan control system. The calculation method comprises the following steps: receiving a rotating speed information; converting the rotating speed information into a first two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of M to generate a second two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of P to generate a third two-digit rotating speed information; adding the second two-digit rotating speed information and the third two-digit rotating speed information to generate a fourth two-digit rotating speed information; and generating a rotating speed count signal according to a first system clock frequency and a working period intermediate value by using a counter.

The application discloses a kind of sensor signal active fault-tolerant control system for strong electromagnetic pulse environment, belong to digital control fault-tolerant technical field.System includes the pre-processing module, signal identification module, pseudo-cluster separation module and signal reconstruction module connected in turn.Pretreatment module carries out FIR low-pass filtering to original sensor signal;Signal identification module generates abnormal flag by sliding window difference and energy mutation monitoring;Pseudo-cluster separation module carries out pseudo-cluster to continuous abnormal flag by finite state machine, and outputs interference section mask;Signal reconstruction module reconstructs signal to interference section based on mask, using local autoregressive prediction model.The scheme can identify and reconstruct sensor signal distorted due to strong electromagnetic pulse interference in real time and efficiently, significantly improve the reliability and robustness of digital control system such as aero-engine in complex electromagnetic environment, and is particularly suitable for FPGA platform implementation.