Reed-Solomon code decoder

Abstract

The invention discloses a Reed-Solomon code decoder (12), which comprises the following parts from input to output connected electrically: adjoint calculating mode, MEA algorism mode (22), money searching mode (23), Funi algorism mode (24) and correction output mode (25) and data buffer mode (26) between the output end and correction output mode, wherein the input is multi-byte bus input; the MEA algorism mode contains one or more paralleling 8-bit MEA algorism submode (41) between calculating mode and money searching mode, which divides time and processes respective 16-bit data through consolidating to halve each iterative time. The decoder saves resource because the broad bus band is more than 1 byte, which reduces the designing difficulty.

Description

technical field [0001] The invention relates to digital optical fiber communication, in particular to a Reed-Solomon (referred to as RS) code decoder. Background technique [0002] In current digital optical fiber communication systems, forward error correction technology has been widely used. In optical fiber communication systems, FEC is first applied to submarine cable communication systems. The G.975 proposal promulgated by ITU-T in 1996 adopted the FEC function as a part of the submarine cable communication standard. In the new draft passed in April 2000, the FEC function of the 10Gbit / s system was added as an option. Since the bandwidth bottleneck has been shifted from the backbone network to the access part, FTTx technology is increasingly becoming a hot technology in the communication network. Among the technologies adopted by FTTH, the passive optical network (PON) technology is the most promising technology. In the current PON technology, the two most attractive...

AI Technical Summary

Problems solved by technology

But adopt this technology in GPON now, there are following problems: 1) the data bus of a byte broadband is adopted in the accompanying formula calculation module, and realize in the Field Programmable Gate Array (FPGA) often adopt wider bus to reduce the clock rate

2) The ME algorithm module for solving key equations occupies the most logical resources. In the case of a 32-bit bus, four parallel processing modules are used, which consumes a lot of resources.

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