57results about How to "Reduce encoding delay" patented technology

Perceptual audio codecs make use of filter banks and MDCT in order to achieve a compact representation of the audio signal, by removing redundancy and irrelevancy from the original audio signal. During quasi-stationary parts of the audio signal a high frequency resolution of the filter bank is advantageous in order to achieve a high coding gain, but this high frequency resolution is coupled to a coarse temporal resolution that becomes a problem during transient signal parts by producing audible pre-echo effects. The invention achieves improved coding / decoding quality by applying on top of the output of a first filter bank a second non-uniform filter bank, i.e. a cascaded MDCT. The inventive codec uses switching to an additional extension filter bank (or multi-resolution filter bank) in order to re-group the time-frequency representation during transient or fast changing audio signal sections. By applying a corresponding switching control, pre-echo effects are avoided and a high coding gain and a low coding delay are achieved.

A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M>=8, N>=4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.

The invention relates to encoding and decoding methods for shortening a Turbo product code. The encoding method comprises the following steps of: performing row or column encoding on an information sequence to be encoded; performing parallel encoding on code words of row or column component codes generated by the row or column encoding; and judging whether the encoding is finished. The decoding method comprises the following steps of: generating a hard decision sequence of a soft-input information sequence; selecting the least reliable bits in the soft-input information sequence; generating a test sequence according to the hard decision sequence and the least reliable bits; decoding the test sequence to generate candidate code words; calculating the measurement of the candidate code words and the soft-input information sequence; reducing the number of the candidate code words; determining decision code words according to the measurement of the candidate code words; and calculating external information of each code element in the decision code words. The encoding method has the advantages of improving data throughput and reducing encoding delay; and the decoding method has the advantages of saving a mass of logical resources and storage resources, particularly well balancing decoding complexity and data throughput under the condition of longer code length of component codes.

The invention discloses an encoder of an LDPC code with a layered quasi-cyclic extension structure, comprising: an input buffer, a first processing-buffering pipeline stage, a second processing pipeline stage, a third buffering pipeline stage, and a fourth processing-buffering pipeline stage and output stage, according to the characteristic that the parity check matrix H is a quasi-cyclic shift matrix splicing, the pipeline structure of the RU coding method is simplified, the number of pipeline stages is reduced from six to four, and the coding delay is shortened. At the same time, according to the implementation characteristics of the main functional modules, the maximum pipeline delay is reduced and the encoding throughput is improved. Then, according to the characteristics of the quasi-cyclic shift matrix operation, the resource consumption of the encoder ROM was reduced, and the sparse matrix multiplication vector in the RU method was replaced by the quasi-cyclic shift unit matrix multiplication vector, and the quasi-cyclic shift matrix multiplication vector was used instead of Non-sparse matrix-by-vector in RU methods. In order to meet the requirements of variable code length and variable code rate, the ping-pong RAM between stages can reserve a large storage space.

The invention discloses a background modeling-based static camera video compression method and a background modeling-based static camera video compression system. The method comprises the following steps: for an input video sequence, selecting a training image set and modeling the selected training image set to generate a background image; adopting a coder to encode and compress the background image to generate a background image code stream; adopting a decoder to decode and reconstruct the background image code stream to acquire a reconstructed background image; differentiating images in theinput video sequence and the reconstructed background image, calculating a differentiation result and acquiring a differential image according to the differentiation result; and encoding and compressing the differential image. In the method and the system, a fixed scene part and other parts of video are compressed respectively by utilizing the characteristic that a scene of the video sequence is fixed and establishing and updating a model describing the relatively fixed scene in the video so as to eliminate redundancy in the video sequence to a greater extent to obtain better compression performance.

The invention discloses a check bit generator based on a double-diagonal quasi-cyclic shift low-density check code, relates to an encoding device, and mainly solves the problems of high complexity and long encoding time delay of the existing encoder. The whole device includes a pre-coded storage unit and a check bit generating unit. The pre-coded storage unit is used to store pre-coded data. It includes a front-end modulo two adder Σ' and a plurality of parallel dual-state shift registers. Each dual-state The shift register is composed of a two-to-one selector and a plurality of D flip-flops connected in sequence; the check bit generation unit is used to generate check bits, and it is composed of m-1 back-end modulo two adders Σ. The output data of the precoding storage unit is transmitted to the check bit generation unit, and the check bit is output by the check bit generation unit. The invention has the advantages of simple structure and high encoding efficiency, and is used as a device of an LDPC encoder.