56results about How to "Reduce encoding delay" patented technology

A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M>=8, N>=4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.

The present invention discloses a coder of LDPC code used in hierarchical quasi-cyclic expansion structure, comprising an input cache, a first depositing and caching pipeline grade, a second depositing pipeline grade, a third caching pipeline grade, a fourth depositing and caching pipeline grade and an output grade. By utilizing the character that the check matrix H is formed by connecting the quasi-cyclic sift matrix, the present invention simplifies the pipeline structure of the RU coding method, reduces the grades of the pipeline from sixth grade to fourth grade, and shortens the coding delay. Besides, the present invention decreases the largest pipeline delay and increases the coding thuoughput according to the fulfilling character of the main functional module. And the present invention also reduces the energy consumption of the coder ROM according to the operational character of the quasi-cyclic sift matrix; replaces the sparse matrixmultiply vector in the RU method with the quasi-cyclic sift unit matrix multiply vector; and replaces the non sparse matrix multiply vector in the RU method with the quasi-cyclic sift matrix multiply vector. A larger storing space can be remained in the ping pong RAM amid the grades to fit the demand of the variable length code and the VBR.

The invention relates to encoding and decoding methods for shortening a Turbo product code. The encoding method comprises the following steps of: performing row or column encoding on an information sequence to be encoded; performing parallel encoding on code words of row or column component codes generated by the row or column encoding; and judging whether the encoding is finished. The decoding method comprises the following steps of: generating a hard decision sequence of a soft-input information sequence; selecting the least reliable bits in the soft-input information sequence; generating atest sequence according to the hard decision sequence and the least reliable bits; decoding the test sequence to generate candidate code words; calculating the measurement of the candidate code wordsand the soft-input information sequence; reducing the number of the candidate code words; determining decision code words according to the measurement of the candidate code words; and calculating external information of each code element in the decision code words. The encoding method has the advantages of improving data throughput and reducing encoding delay; and the decoding method has the advantages of saving a mass of logical resources and storage resources, particularly well balancing decoding complexity and data throughput under the condition of longer code length of component codes.

The invention discloses video encoding/decoding method and system based on background modeling and an optional differential mode. The encoding method comprises the following steps of: modeling and generating a background image by using an input video sequence, and encoding to obtain a reconstructed background image; carrying out pixel or sub-pixel accuracy global motion estimation on each input image to obtain a global motion vector; and carrying out encoding on each video block by selectively using an original mode and a differential mode on the basis of the reconstructed background image and the global motion vector. The invention can improve the encoding performance and has the advantages of not increasing the encoding delay and being beneficial to further processing as the code streamcontains the background image per se.

Method and arrangement in a network node for adapting a property of source coding to the quality of a communication link in packet switched conversational services in a communication system. The method comprises obtaining (404) information related to the quality of a communication link. The method further comprises selecting (406) a source coding mode with an associated source coding delay, based on the obtained information and the associated source coding delay. The selected source coding mode is selected from a set of at least two source coding modes associated with different source coding delays, and is to be used when source coding voice data to be transmitted over the communication link.

The invention discloses a method for reducing video coding time delay, so as to effectively reduce coding time delay in image video coding. The method comprises steps that: two video frame buffers are placed in handling the video coding, one frame of image data is collected by each video frame buffer in turns, one video frame buffer collects one frame of image data and the other video frame buffer collects the next frame of image data; and when CPU completes the video coding of one frame of image in one video frame buffer, the CPU continues to handle the video coding of the next frame of image in the other video frame buffer and the work is cycled.

The invention provides a data parallel encoded processing device in order to realize the parallel processing of LTE (Long Term Evolution) Turebo encoding. The device comprises a first parallel encoder, an inner interweaver and a second parallel encoder, wherein the first parallel encoder is used for carrying out parallel encoded processing on M bits of input data input from a first path; the inner interweaver is used for carrying out interwoven processing on M bits of data input from a second path parallel to the first path; and the second parallel encoder is used for receiving data subjected to the interwoven processing and carrying out parallel encoded processing on the data subjected to the interwoven processing, wherein M is equal to 2m, m is an integer being larger than 0 and smaller than 13, and the total bits of the input data can be divided by M with no remainder. In addition, the invention also provides a method for carrying out encoded processing on the data in order to realize the parallel processing of the LTE Turebo encoding.

The invention discloses an encoder device for a short code length multi-system weighted repeat-accumulate code. The device comprises an input information symbol cache unit, a coding arithmetic unit and an output code symbol cache unit which are connected with a control circuit respectively, the control circuit comprises an input control counter, a master control counter and an output control counter which are sequentially connected, a counting signal a output by the master control counter is connected with logic and gate though a counting comparator, a gate signal g output by the master control counter is respectively connected with the logic and gate and the output code symbol cache unit, output of the logic and gate is connected with the input information symbol cache unit and the coding arithmetic unit, output of the output control counter is connected with the output code symbol cache unit, the coding arithmetic unit comprises a weighted repeat-accumulate arithmetic unit, a weighted accumulating unit and a selector which are sequentially connected, and the selector is directly connected with a signal input end of the coding arithmetic unit. According to the encoder device for the short code length multi-system weighted repeat-accumulate code, the complexity and coding delay have a linear relation with the code length, the achieving mode is simple, and the device is convenient to apply to the communication system.

The invention discloses a monitoring video-oriented high-efficiency video coding standard quantization parameter cascading method. The method comprises the steps: determining and encoding quantizationparameters of a first frame, determining and encoding quantization parameters of first two image frames, determining an optimal reference frame probability of a second image frame, determining an average standard deviation between the first frame and the first two image frames, determining parameters related to frame distortion, determining parameters related to a frame code rate, determining anaverage inter-frame difference of the first two image frames, determining parameters of an inter-frame reference frame, determining Newton-Raphson parameters, determining a quantization parameter offset greater than or equal to a quantization parameter offset of a third image frame, and encoding a frame greater than or equal to the third image frame. The method solves the problems that in the prior art, coding dependence between video frames is not comprehensively considered, model parameter acquisition in the prior art is complex, and the method is not suitable for monitoring video coding. The method has the advantages of high coding rate distortion performance, simple model parameter calculation, small coding time delay and the like, and can be applied to the technical field of monitoring video coding.

The invention discloses a high-performance polarization encoding method and encoder for satellite discontinuous communication, and the method comprises the steps: S1, dividing a polarization code freezing bit and an information bit into a plurality of code blocks, carrying out the polarization encoding of each code block, storing the information bit in an ROM1, and storing the polarization encoding in an ROM2; S2, addressing the ROM2 by utilizing the position information of the information bits stored in the ROM1; s3, performing bitwise exclusive OR on a result obtained by performing bitwise exclusive OR on a certain row output by the ROM1 and the data read from the FIFO at the moment and a data result stored in the register REG, and storing an obtained numerical value back to the registerREG; and S4, writing an encoding result in the step S3 into an RAM, and starting polarization encoding of the next group of code lengths after the REG of the register is reset. And in the second part, XOR operation is carried out on the code block coded in the first part according to the butterfly graph. FPGA hardware resources consumed by the encoder are extremely low; the encoding time delay ofthe encoder is extremely low; the encoder throughput rate is high.

The invention belongs to the technical field of redundant term error detection or forward error correction for data expression, and discloses an IEEE802.11n LDPC (Low Density Parity Check) encoding system and method. The system comprises a Z-bit register module, a parameter control module, a barrel-shaped displacement module, a check bit p0 calculation module, an encoded middle information lambdacalculation module, a check bit pi calculation module, a check bit pi' calculation module, an information bit mj and check bit pi cache module, a check bit pi' cache module and a code output module. By adding of a dual-input xor summator and a register, parallel encoding of two paths of an encoder can be achieved, and the encoding time delay of an LDPC encoder is substantially shortened, so that increase of the throughput rate is realized. According to the IEEE802.11n LDPC encoding system, by use of the parallel calculation idea, a little hardware resource consumption is increased, but the throughput rate of the encoder is substantially increased. The used encoding algorithm is low in complexity, high in throughput and suitable for hardware implementation.

An embodiment of the invention provides a video image processing method and device and a server, and relates to the technical field of cloud computing. The video image processing method is characterized in that a server encodes a first frame image in a target video image into an internal encoding frame and encodes frame images after the first frame image in the target video image into forward prediction frames, and the internal encoding frame and the forward prediction frames form the encoded target video image. On one hand, only the first frame image is coded into the internal encoding frame, so that the number of the internal encoding frames after encoding can be reduced, and the data volume of the target video image after encoding is further reduced; and on the other hand, the frame images after the first frame image are all coded into the forward prediction frames, and the bidirectional interpolation frames are not encoded, so that the encoding delay can be reduced during encoding. Therefore, the network requirement threshold of a client for using a cloud application can be reduced, and good cloud service can be obtained even under the condition that the real-time network speed is lower than the current cloud application requirement.

The embodiment of the invention discloses a video coding method and device, equipment and a storage medium, and belongs to the technical field of digital signal processing. The method comprises the following steps: acquiring a target image frame to be coded; under the condition that the number of the reference image frames of the target image frame does not meet the analysis condition, determining a frame type and a coding parameter of the target image frame according to a first mode, wherein the first mode is a mode in which the frame type and the coding parameter are determined not according to the reference image frame; and coding the target image frame according to the frame type and the coding parameter of the target image frame. According to the method, the waiting process that the coding device obtains the enough number of reference image frames under the condition that the number of the reference image frames of the image frame to be coded does not meet analysis is eliminated, the waiting time of the coding device is shortened, excessive parameters and complex calculation modes do not need to be introduced, and the coding time delay can be effectively reduced.

The invention discloses an FEC coding IP core for an LEO satellite VCM data transmission system. The FEC coding IP core comprises an input cache module, a BCH coding module, an LDPC coding module, a parallel bit interleaving module and an output cache module, wherein the input cache module is used for receiving and caching to-be-coded information bits and VCM mode parameters set by a user; the VCMmode comprises a code rate R, a coding frame length L and a modulation mode; the BCH coding module is used for performing BCH coding on the kbch information bits according to a DVB-S2 standard, generating a code word with the length of nbch, and transmitting coded information to the LDPC coding module; the LDPC coding module is used for performing LDPC coding on the kldpc information bits according to a DVB-S2 standard to generate a code word with the length of nldpc; kldpc is equal to nbch, nldpc is equal to L, and the information bits and check bits are output to the parallel bit interleaving module in parallel in sequence; and the parallel bit interleaving module is used for realizing row and column interleaving required by a modulation mode in the DVB-S2 standard, and the coded and interleaved code words are transmitted to the output cache module in a symbol form for caching.

The invention provides a high-efficiency low-time-delay kinesthetic signal encoder and decoder and a coding and decoding method. The encoder is composed of a signal amplifier, a discrete cosine transform module, a quantizer, a run length encoding module and an entropy encoder; the decoder is composed of an entropy decoder, a run length decoding module, an inverse quantizer, an inverse discrete cosine transform module and an inverse amplifier. Compared with an existing advanced tactile coding method, the high-efficiency low-time-delay kinect signal encoder and decoder design provided by the invention has the advantages that the compression ratio is averagely reduced by 50% in comparison with a tactile coding standard algorithm based on a dead zone, and meanwhile, the distortion degree and the time delay are smaller.

The invention discloses an ultra-low time delay H.264 coding method and coder, and relates to the field of video signal coding. According to the technical scheme, the ultra-low time delay H.264 coding method comprises the steps of preprocessing input video, conducting cache on multiple video lines in the preprocessed video, conducting frame prediction on the multiple video lines, conducting DCT coding and quantization on frame prediction results in sequence, conducting entropy coding on a quantization result and a motion vector, outputting the result of the entropy coding after the result is buffered and the like.