Check Digit Generator Based on Double Diagonal Quasi-Cyclic Shift Low Density Check Code

A low-density check code and check bit technology, applied in error detection coding using multi-bit parity check bits, error correction/detection using block codes, digital transmission systems, etc. The problem of high encoder complexity can achieve the effect of improving throughput, reducing encoding complexity, and reducing encoding delay.

Inactive Publication Date: 2012-02-08
XIDIAN UNIV
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Problems solved by technology

[0007] The purpose of the present invention is to provide a check digit generator based on a double-diagonal quasi-cyclic shift low-density check code, to solve the problems of high complexity of the encoder and large encoding delay, and to achieve fast encoding

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  • Check Digit Generator Based on Double Diagonal Quasi-Cyclic Shift Low Density Check Code
  • Check Digit Generator Based on Double Diagonal Quasi-Cyclic Shift Low Density Check Code
  • Check Digit Generator Based on Double Diagonal Quasi-Cyclic Shift Low Density Check Code

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Embodiment Construction

[0021] Reference figure 1 The check digit generator of the present invention is mainly composed of a pre-coded bit storage unit and a check digit generation unit. The pre-coded storage unit is used to store pre-coded bit data. It has a state selection port and a pre-coded bit input Port and a data output port; the check bit generation unit is used to generate the check bit of the low-density check code, and it is provided with a data input port and a check bit output port. The data output port of the precoding bit storage unit is connected to the data input port of the check digit generating unit, and the check bit output port of the check digit generating unit is used as the check bit output port of the entire check digit generator.

[0022] Reference figure 2 The said precoding storage unit is composed of a front-end modulus two adder Σ′ and m+1 parallel bi-state shift registers of length z, each bi-state shift register is composed of a two-to-one selector and z D flip-flops a...

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Abstract

The invention discloses a check bit generator based on a double-diagonal quasi-cyclic shift low-density check code, relates to an encoding device, and mainly solves the problems of high complexity and long encoding time delay of the existing encoder. The whole device includes a pre-coded storage unit and a check bit generating unit. The pre-coded storage unit is used to store pre-coded data. It includes a front-end modulo two adder Σ' and a plurality of parallel dual-state shift registers. Each dual-state The shift register is composed of a two-to-one selector and a plurality of D flip-flops connected in sequence; the check bit generation unit is used to generate check bits, and it is composed of m-1 back-end modulo two adders Σ. The output data of the precoding storage unit is transmitted to the check bit generation unit, and the check bit is output by the check bit generation unit. The invention has the advantages of simple structure and high encoding efficiency, and is used as a device of an LDPC encoder.

Description

Technical field [0001] The present invention belongs to the field of communication, and relates to coding technology, in particular to a component of an LDPC code encoder that can realize fast coding. Background technique [0002] In modern digital communication systems, in order to ensure the reliable and effective transmission of various data, error correction coding techniques are often used. In recent years, with the development of wireless digital communications and the emergence of various high-speed data services, it has become more and more important to study and use error correction coding technology. [0003] Theoretical research shows that the performance of the LDPC long code of the low density parity check code exceeds the Turbo code and is close to the Shannon limit. It also has linear decoding complexity and is suitable for high-speed data transmission. In the development process of LDPC codes from theoretical research to practical applications, the coding complexit...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11H04L1/00
Inventor 李颖郭旭东马卓孙岳
Owner XIDIAN UNIV
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