201 results about "Bch coding" patented technology

In transmitter apparatus for a digital television (DTV) broadcasting system, internet-protocol (IP) packets of digital television information are subjected to multilevel concatenated Bose-Chaudhuri-Hocquenghem (BCH) coding and low-density parity-check convolutional coding (LDPCCC) before being bit-interleaved and mapped to quadrature-amplitude-modulation (QAM) constellations. The QAM constellations are used in coded orthogonal frequency-division modulation (COFDM) of plural carrier waves up-converted to a radio-frequency broadcast television channel. In receiver apparatus for the DTV broadcasting system the results of de-mapping QAM constellations recovered from demodulating the COFDM carrier waves are de-interleaved, and the constituent LDPCCC codewords are decoded to recover constituent BCH codewords of the multilevel BCH coding. The constituent BCH codewords are decoded to correct remnant bit errors in them. Then, IP packets of digital television information are reconstituted from the systematic data bits in those BCH codewords.

A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received polynomial. The processing then continues by converting the received polynomial into a plurality of error identifying polynomials. The processing then continues by recursively processing the plurality of binary error identifying polynomials to produce a plurality of error identifying values. The processing then continues by processing the plurality of error identifying values to produce an error locator polynomial that represents error in the received polynomial. The processing then continues by evaluating the error locator polynomial to identify the bit location of the error in the BCH encoded signal. The processing then continues by correcting the BCH encoded signal based on the bit location of the error.

Systems and methods for constructing concatenated codes for data storage channels, such as holographic storage channels, are provided. The concatenated codes include an outer BCH code and an inner iteratively decodable code, such as an LDPC code or turbo code. The correction power and coding rate of one or both of the codes may be programmable based on the channel characteristics and the desired SNR coding gain. The correction power and/or coding rate of the inner and/or outer code may also be dynamically adjusted in real-time to compensate for time-varying error conditions on the channel.

A system and method are provided for coding a frame in a packet communications system using a G.709 Digital Wrapper Frame format. The method comprises: accepting digital information; outer encoding the digital information with a Reed Solomon (RS) encoding scheme; interleaving the outer encoded information; inner encoding the interleaved information using a BCH encoding scheme; and, forming a G.709 Digital Wrapper frame including payload and parity bytes. More specifically, a standard DW superframe is formed with 122,368 bits of payload and 8192 bits of parity. The outer encoding process uses an RS(1023,1007) parent code. In one aspect, 15 groups of RS(781,765) and 1 group of RS(778,762) codewords are formed per superframe. The inner encoding process uses a BCH(2047,1959) parent code. In one aspect, 64 groups of BCH(2040,1952) codewords are formed per superframe.

This invention relates to earth digital television broadcast coding method in digital information transmission technique field, which comprises the following steps: diving transmission flow into 752 bit set and adding 261 zeros to get 1013 bit for BCH coding and removing front 261 bit to get BCH(762,752); forming one set of BCH(762,752) with certain number to generate matrix of LDPC(7493,3048),LDPC(7493,4572) or LDPC(7493,6096); deleting output 7493 bit front five correction bit to get final 7488 output bit.

Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

The invention discloses an encoding method of a channel error correcting code BCH code and an RS code, belonging to the digital communication field, which comprises calculating an adjoint polynomial S(x) through a received code R(x), solving the Berlekamp key equation through the Euclid algorithm to obtain an error location polynomial sigma (x), and correctly encoding if the constant term sigma 0 in the error location polynomial sigma (x) is zero, or calculating the error locations and the relative error values through the Chien search if the constant term sigma 0 in the error location polynomial sigma (x) is not equal to 0, and being able to correctly encode if the number of searched error locations is equal to the largest error correcting capability thereof, or sending a warning indication signal whose error number of receiving signals exceeds the largest error correcting capability, and outputting original receiving codes. The encoding method avoids the condition that the more errors are corrected, the more errors existing when the receiving code error number exceeds the largest error correcting capability of the channel error correcting code, thereby reducing the error code rate of the whole communication system.

An efficient coding and modulation system for transmission of digital data over plastic optical fibres is disclosed. The digital signal is coded by a three-level coset coding. The spectral efficiency of the system is configurable by selecting the number of bits to be processed in each of the levels. The first level applies to the digital data a binary BCH coding and performs coset partitioning by constellation mapping and lattice transformations. Similarly, second level applies another binary BCH coding, which may be performed selectably in accordance with the desired configuration by two BCH codes with substantially the same coding rate, operating on codewords of different sizes. The third level is uncoded. The second and third levels undergo mapping and lattice transformation. After an addition of the levels, a second-stage lattice transformation is performed to obtain a zero-mean constellation. The symbols output from such three-level coset coder are then further modulated.

An embodiment of the invention relates to a BCH encoder formed with linear feedback shift registers (LFSRs) to form quotients and products of input polynomials with irreducible polynomials of a generator polynomial g(x) of the BCH encoder, with and without pre-multiplication by a factor x^m. The BCH encoder includes multiplexers that couple LFSR inputs and outputs to other LFSRs depending on a data input or parity generation state. The BCH encoder can correct up to a selectable maximum number of errors in the input polynomials. The BCH encoder further includes LFSR output polynomial exponentiation processes to produce partial syndromes for the input data in a syndrome generation state. In the syndrome generation state the LFSRs perform polynomial division without pre-multiplication by the factor x^m. The exponentiation processes produce partial syndromes from the resulting remainder polynomials of the input data block.

An efficient coding and modulation system for transmission of digital data over plastic optical fibers with low latency. In particular, the digital signal is coded by means of a two-level coset coding. The first level applies to the digital data a binary shortened BCH coding and performs coset partitioning by means of constellation mapping and lattice transformations. The second level is uncoded but undergoes mapping and lattice transformation. After an addition of the two levels, a second-stage lattice transformation is performed so as to obtain a zero-mean constellation. The symbols output from such three-level coset coder are then further modulated.

The invention belongs to the field of digital communication and digital storage, and discloses a packet Markov superposition coding method by taking a binary BCH code as a component code, and a decoding method. The binary BCH code having the code length of n, the information bit length of k and the error correcting capability of tmin is used as the component code; and a binary information sequence (u)u(/u) having the length of K=kBL is coded into a code (u)c(/u) having the length of N=nB(L+m). The invention further provides a soft iteration decoding method applicable to the packet Markov superposition coding method by taking the binary BCH code as the component code. The soft iteration decoding method comprises the following steps of: generating a turnover pattern according to a tree structure, judging whether a test process is ended or not and whether soft information output is calculated or not by using the lower bound of the unreliability of a potential legal error pattern, etc. According to the packet Markov superposition coding method and the decoding method thereof provided by the invention, the value of the coding memory length m is {1,2,3}; the net coding gain, which is greater than 10 dB, is provided at the bit error rate performance, which is as low as 10-10 to 10-15; and thus, the packet Markov superposition coding method and the decoding method thereof provided by the invention can be applied to a communication system having low bit error rate requirements, such as optical fibre communication.

A forward error correcton coding method comprises a generalized concatenated code comprising a plurality of outer component codes and a plurality of inner component codes. The outer components codes comprise Reed-Solomon codes and a plurality of binary codes of equal length but varying rates. The inner component codes have a nested structure and are defined by the sum of disjoint Bose-Chaudhuri-Hocquenghem (BCH) codes. The inner and outer component codes are selected such that the product of the minimum Hamming distances of the inner and outer component codes are as equal as possible. Moreover, the component codes are selected by matching cyclotomic cosets of inner BCH codes and type and multiplicity of outer codes.

The invention discloses a super forward error correction hardware decoding method and an apparatus thereof. The hardware decoding method of the invention comprises the following steps of: adopting BCH (2040, 1952) code for calculating the syndrome of reception channel output data and solving the error position polynomial thereof; carrying out money search to determine the code element error position among BCH code words and accordingly correct the error, and completing decoding processing of the code elements of BCH code words one by one; carrying out interlacing processing every time the decoding of each internal code BCH code element is processed, calculating RS code word syndrome of the decoding result, solving error position polynomial and error value polynomial, carrying out money search according to the error position polynomial, determining the code element error position of the RS code word, calculating error value according to the error value polynomial and conducting error correction, completing the decoding of the code elements of RS code word one by one; and carrying out deinterlacing on output data, thereby obtaining SFEC decoding result. The invention can correctly realize the whole algorithm with hardware circuit of relatively small scale and improve the realization sequential speed of SFEC hardware.

The invention provides a signaling coding method and a signaling coding system based on BCH code and short LDPC code cascading. The method comprises the following steps: establishing a zero padding group table of the correspondence between the sequences of zero padding groups divided in turn and the positions of the zero padding groups based on a default LDPC code check matrix and establishing a punching group table of the correspondence between the sequences of punching groups divided in turn and the positions of the punching groups based on the default LDPC code check matrix; zero-padding an input signaling after scrambling treatment according to the zero padding group; sequentially calculating the BCH code check bit and the LPDC code check bit corresponding to the signaling after zero padding based on preset BCH code and LPDC code error correction coding parameters; and determining the number of punching bits of the LPDC code check bit based on the preset linear relationship between the code length of the signaling and the number of punching bits, and punching the LDPC code check bit according to the number and according to the punching group table.

The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.

The invention discloses a real-time streaming media transmission protocol stack in a multi-hop network. A packet control layer and an error control layer are added to an existing transmission control protocol (TCP)/internet protocol (IP) stack. The real-time streaming media transmission protocol stack in the multi-hop network has the advantages that an IP header and a TCP header are compressed by the packet control layer, and the obtained compressed headers reduce data redundancy; the compressed headers are subjected to broadcast channel (BCH) encoding, the encoded headers are uniformly distributed to data portions, the resistance to burst interference of the headers is improved, a receiver can obtain accurate header information through BCH decoding, thereby packet loss and retransmission are avoided, and time delay caused by retransmission is reduced; and a cyclic redundancy check (CRC) single bit error correction based reed-solomon (RS) errors-and-erasures correcting encoding and decoding scheme of the error control layer is utilized, the good communication effect can be guaranteed under the channel with short burst as a majority and accompanied with a small quantity of random errors, and the time delay is excellently controlled.

The invention discloses a BCH code error correction method capable of adaptive error correction, which belongs to the field of data error correction in non-volatile memories. The method comprises the following steps: 1) when a page programming erasing number of a NAND flash memory is less than or equal to a, selecting a sector-level BCH code as an error correcting code; 2) when the page programming erasing number of the NAND flash memory is more than a and less than b, selecting a page-level BCH code as an error correcting code; 3) when the page programming erasing number of the NAND flash memory is more than or equal to b, marking the page as an invalid page. The beneficial effect of the invention is that: when a sector-level BCH code is adopted, the response speed of the flash memory to a host is increased; when a page-level BCH code is adopted, the error correction performance is improved, and thus the service life of the flash memory is increased.

The invention discloses a method for encoding and modulating a logical frame signaling channel in an NGB-W system. The method comprises the following steps of: adding CRC (cyclic redundancy code) bits to logical frame signaling and dividing the logical frame signaling into blocks; scrambling the logical frame signaling block; mapping the scrambled logical frame signaling block into BCH (Broadcast Channel) code information bits; performing forward error correction coding to the BCH code information bits; generating the coding block of the logical frame signaling block; generating logical frame signaling coding bit sequences; generating bit interleaving blocks; performing constellation mapping to the bit interleaving blocks to generate BICM (Bit Interleaved Coded Modulation) blocks. According to the method, the logical frame signaling with any length can be transmitted, so that the different-length logical frame signaling is basically uniform in transmission reliability; four levels of transmission reliability and transmission efficiency are selected under each modulating method.

This invention discloses a BCH decoder for correcting double errors quickly working on GF(25) composed of an ad-joint computing circuit, an error number judgment circuit and an error location computing circuit connected sequently. The BCH code is BCH (N, N-10), code length N is any integer in 11-31. This method utilizes the feature of BCH code of correcting double mistakes to present a search method to compute the error location from the ad-joint result without the help of Chien method or ROM.

The invention discloses an FPGA-based BCH encoding and decoding method comprising the following steps: a receiving module receives signal data and sends the signal data to a BCH encoding module, the BCH encoding module encodes the signal data in a segmented manner to get r bit check digits corresponding to the signal data, and the signal data and the bit check digits are stored in a storage module; after the signal data and the parity bits are acquired from the storage module, BCH decoding is performed to get a code word polynomial R(x), Q syndromes of the code word polynomial R(x) are obtained on the basis, and an error location polynomial of error of the signal data in the storage process is obtained; and the root of the error location polynomial is solved according to the error location polynomial of error of the signal data in the storage process and a money search traversal algorithm, and the error data bit of the signal data in the storage process is corrected to get correct signal data stored in the storage module.