39 results about "Bch coding" patented technology

The present invention belongs to the technical field of decoding algorithms, and specifically relates to normalized minimum sum decoding of BCH codes and post-processing decoding methods thereof, the steps of which include optimizing the standard form of the check matrix of the BCH code to obtain the best check matrix; inputting the received sequence into the improved normalized minimum sum decoding algorithm NMS based on the best check matrix for decoding; if the decoding is successful, outputting the best decoding estimate; if the decoding fails, inputting the sequence iteration trajectory after the NMS decoding failure into the DIA neural network model, analyzing and outputting the reliability metric of each bit, and then decoding again through the ordered statistical decoder OSD to obtain the best decoding estimate. The present invention successfully achieves the low density of the check matrix, the reduction of the number of short loops, and the uniform distribution of column weights through an innovative check matrix optimization algorithm, and provides a more efficient and better performance BCH code decoding solution.

The invention belongs to the technical field of decoding algorithms, and particularly relates to a normalized minimum sum decoding and post-processing decoding algorithm of a BCH code, which comprises the following steps of: for the BCH code, optimizing a check matrix in a standard form of the BCH code to obtain an optimal check matrix; inputting the receiving sequence into an improved normalized minimum sum (NMS) decoding algorithm based on the optimal check matrix for decoding; if the decoding is successful, outputting the optimal decoding estimation; and if the decoding fails, inputting a sequence iteration track after the NMS decoding fails into the DIA neural network model, analyzing and outputting the reliability measurement of each bit, and then decoding again through an ordered statistical decoder OSD to obtain the optimal decoding estimation. Through an innovative check matrix optimization algorithm, low density of the check matrix, reduction of the number of short rings and uniform distribution of column weights are successfully realized, and a BCH code decoding scheme which is more efficient and better in performance is provided.

The present invention belongs to the technical field of BCH code decoding, and specifically relates to an error correction decoding method based on BCH codes. The steps include constructing a neural network model suitable for UDE detection. If the output result is approval, decoding ends; otherwise, it is determined to be an undetectable decoding error (UDE), triggering an ordered statistical decoder (OSD) for further decoding; constructing a DIA correction model to improve the bit reliability metric of the received sequence before OSD decoding; using the ALMLT algorithm to obtain the order of test error patterns as the initial value of the OSD decoding path, and then obtaining the frequency distribution characteristics of the actual error pattern or estimated error pattern corresponding to the decoded codeword, continuously fine-tuning the order of the test error patterns, obtaining an optimized decoding path, and performing OSD decoding on the BCH code. The present invention significantly improves the reliability and efficiency of BCH codes in NMS decoding, while reducing computational complexity and latency.

The embodiment of the invention discloses a data processing method and a related device. Specifically, for a first data stream subjected to outer code coding, the first data stream is subjected to inner code coding to obtain a second data stream comprising at least one inner code word. Wherein the inner code coding adopts GF (28) error correction 2-bit extended BCH coding, the inner code codeword comprises 119 information bits and 17 check bits, the total number of the bits is 136, and the 17 check bits comprise 1-bit CRC extended check bit. That is to say, the embodiment of the invention adopts single-bit extended BCH (136, 119) coding with 2 bits of error correction capability. In an existing 400G ZR scene, data filling and convolutional interleaving between outer code coding and inner code coding are realized by taking 119 bits as granularity, so that the inner code coding scheme provided by the embodiment of the invention is compatible with the 400G ZR scene, and meanwhile, the cascade coding performance is also improved.

The invention belongs to the technical field of BCH code decoding, and particularly relates to an error correction decoding method based on a BCH code, which comprises the following steps: constructing a neural network model suitable for UDE detection, if an output result is approved, ending decoding, otherwise, judging that decoding error UDE cannot be detected, and triggering an ordered statistical decoder OSD for further decoding; constructing a DIA correction model, and improving the bit reliability measurement of a received sequence before OSD decoding; an ALMLT algorithm is utilized to obtain a sequence of test error modes, the sequence is used as an initial value of a decoding path of the OSD, then frequency distribution characteristics of a real error mode or an estimated error mode corresponding to a decoding code word are obtained, the sequence of the test error modes is continuously finely adjusted, an optimized decoding path is obtained, and OSD decoding is carried out on a BCH code. According to the method, the reliability and the efficiency of the BCH code in NMS decoding are remarkably improved, and meanwhile, the calculation complexity and the time delay are reduced.

Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding / decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

The present invention discloses a digital encoding, decoding and communication method and system based on multilevel coded modulation, which relates to the field of digital communication modulation technology. The encoding method includes: dividing the information sequence to be transmitted into a first-level bit sequence and a second-level bit sequence according to the channel capacity ratio of the 4-PAM modulation system and the code length of the information sequence to be transmitted; performing polar code encoding on the first-level bit sequence to obtain a first-level encoded bit sequence; sequentially performing CCDM distribution matching and BCH code encoding on the second-level bit sequence to obtain a second-level encoded bit sequence; processing the second-level encoded bit sequence based on the first-level encoded bit sequence to obtain a processed second-level encoded bit sequence; and performing 4-PAM modulation on the first-level encoded bit sequence and the processed second-level encoded bit sequence by using a set partitioning mapping rule to obtain a modulation symbol sequence. The present invention improves the ability to reduce the probability of high-energy constellation points and improves the data transmission quality.

The invention provides an Internet of Things data storage method and system based on a BCH code, and belongs to the technical field of data processing, and the method comprises the steps: firstly obtaining and coding an original data packet, and generating a BCH coding data block; then, constructing a storage network topology comprising a plurality of relay nodes and aggregation nodes, and pre-defining a logic association relationship for forming an incomplete connection graph structure for each relay node; distributing the data blocks to the selected part of relay nodes for storage; generating verification information fusing the storage content, the fragment identifier and the associated node information for each storage node; generating a verification path passing through at least two relay nodes based on the topology and logic association relationship; and sequentially acquiring verification information or data fragments of each node along the path, and executing chained verification on the BCH coded data block to complete integrity verification. Through the combination of coding fault tolerance, topological distributed storage and relevance chained verification, the reliability and verification efficiency of data storage of the Internet of Things are improved.

The application discloses a kind of medium wave communication navigation integrated signal design method, comprising: generating frame synchronization code and navigation text;The binary code of navigation text is segmented according to fixed bit length, and segmented binary code is obtained;According to order, segmented binary code is two two as a group, and each group of segmented binary code is first converted into series / parallel, then BHC error correction coding is carried out respectively;For each group of BCH code, parallel / series conversion is carried out according to each bit order to output interleaved code, so as to complete the interleaving coding of navigation text;Interleaved coded navigation text and frame synchronization code are modulated using full hopping MPPSK modulation, framing is carried out, multiple frame signals are formed, the multiple frame signals are used to replace the sine carrier in broadcast signal, and composite modulation signal is generated by composite modulation with analog audio signal and transmitted through broadcast station.The application can realize the dual functions of broadcast and navigation without affecting the normal use of users.

The application relates to a fast frame synchronization method, device and equipment for a Beidou navigation signal and a medium, and relates to the technical field of Beidou satellite navigation. The method comprises the following steps: performing subframe synchronization code sliding matching on a navigation data bit stream of a Beidou navigation signal output by a carrier loop and subjected to bit synchronization, and determining the starting position of a subframe of the Beidou navigation signal; performing three times of BCH checking on the first two words of the subframe according to an error correction coding scheme combining the interleaving technology and the BCH coding adopted by the Beidou navigation signal; if any time of the BCH checking is passed, then performing within-week time and subframe number checking on the first two words of the subframe; if the within-week time and subframe number checking is passed, then completing the subframe synchronization of the Beidou navigation signal; otherwise, re-executing the subframe synchronization code sliding matching until the subframe synchronization is completed. By adopting the method, the subframe synchronization time of the Beidou navigation signal can be significantly reduced, and the reliability and accuracy of the subframe synchronization can be greatly improved.

The invention relates to an integrated circuit and a method for processing a coded message word. The integrated circuit has a receiver designed to receive a message word and an integrated hardware decoding circuit, which has: a calculation unit, which is designed to: calculate a syndrome of the message word according to a preset BCH code, wherein the syndrome has one or more syndrome elements in an extended field of a prime field; a logarithm operator, which is designed to find the logarithm of each syndrome element of the one or more syndrome elements; an arithmetic operation circuit, which is designed to find the logarithm of each zero point of one or more zero points of an error locator polynomial of the BCH code based on the logarithm of the one or more syndrome elements; and a bit inverter circuit, which is designed to invert one or more bits of the message word, whose bits are described by the logarithm of one or more zero points of the error locator polynomial. The integrated circuit also has a data processing circuit, which is designed to further process the message processed by the bit inverter circuit.

The invention belongs to the technical field of communication signal processing and code identification, and solves the problem of channel code identification when a non-cooperative communication system lacks coding parameter prior information and training data with labels. According to the technical scheme, the method is characterized in that a unified recognition framework is constructed based on five features, namely, a rank fluctuation feature is used for distinguishing convolutional codes and linear block codes, a continuous zero spectrum feature is used for recognizing BCH codes, a multi-dimensional structure feature is used for detecting Turbo product codes, a bit distribution deviation feature is used for recognizing polarization codes, and an average absolute column correlation feature is used for distinguishing LDPC codes and non-LDPC codes; blind recognition of five types of channel codes including BCH codes, LDPC codes, convolutional codes, Turbo product codes and polarization codes is achieved. The method does not depend on coding parameter prior information, does not need training, is high in recognition rate under a low signal-to-noise ratio, is high in generalization capability, and is suitable for real-time and resource-limited scenes.

Embodiment herein provide a Bose-Chadhuri-Hocquenghem (BCH) encoder for generating a BCH signal. The BCH encoder (1) includes a memory for storing a minimum distance to be used for generating the BCH signal for a BCH code (n, k) and a polynomial generator for generating a generator polynomial for the BCH code (n, k) and encoding the generator polynomial to obtain the BCH signal. The polynomial generator includes a set of k registers (4) connected in series to receive the information bits and output an encoded bit based on a clock signal, a first gate (5) to receive a code length, a number of information bits, and the minimum distance as input, a second gate (6), and a finite field adder circuit (7) for determining a finite field sum of the output of each register of the set of k registers (4).

Systems and methods are disclosed, including a memory system that includes a memory array and a memory controller. The memory array includes memory cells that are included in multiple memory dies. The memory controller includes a cyclic redundancy check (CRC) encoder configured to determine a CRC code using a data word received by the memory controller; and a Bose-Chaudri-Hocqenghem (BCH) encoder configured to determine a BCH code using the data word and the CRC code. The memory controller is configured to store the data word in the memory array and store the BCH code and the CRC code in the memory array in association with the data word.

This invention provides an efficient parallel encoding and decoding method for BCH codes, belonging to the technical field of BCH encoding and decoding circuit implementation in the areas of memory and error correction coding. Unlike previous lookup table methods, for an (n, k, t) BCH code with an n-bit codeword length, k data bits, and t-bit error correction capability, this invention only needs to store the values ​​of k n-k bit parity check matrix column vectors. These k n-k bit parity check matrix column vectors are then XORed with the S-synonym value for t rounds. The error pattern corresponding to the received codeword is obtained from the bitwise XOR value and corrected. This invention is a hardware-level encoding and decoding implementation, which can be completed within one clock cycle, reducing the multi-cycle decoding delay caused by iterative algorithms, achieving parallelization of BCH encoding and decoding, simplifying the encoding and decoding process, and reducing resource consumption.

The invention discloses a BCH parallel coding and decoding algorithm suitable for eMMC. The BCH parallel coding and decoding algorithm comprises a BCH coding algorithm and a BCH decoding algorithm. The BCH coding algorithm determines a corresponding generator polynomial through a given error correction capability and effective data bits, and further constructs a corresponding BCH code; a BCH decoding algorithm calculates a syndrome to solve an error position polynomial coefficient, and then a root of an error polynomial is solved by using Chien search, so that an error position is obtained and corrected. The BCH coding algorithm adopts an 8-bit parallel coding mode to process the data, so that the coding efficiency is improved; according to the BCH decoding algorithm, a parallel processing syndrome solving module and a Chien search module are adopted, and a block decoding mode of a two-stage pipeline structure is adopted, so that the decoding time is shortened, and the decoding efficiency is improved.

The invention provides a DVB-S2 high-speed parallel BCH code decoder and a decoding method thereof. The decoder comprises an N-path parallel syndrome calculation module, an error polynomial calculation module, an N-path parallel Chien search module and an error correction module. The modules are used for carrying out N-path parallel syndrome calculation on a BCH code to be decoded to obtain a syndrome result; by utilizing an iBM algorithm, performing multiple iterative operations on the syndrome result, and determining an error position polynomial output result; based on the error position polynomial output result, using a small lookup table containing an initial value to determine whether the information position of the to-be-decoded BCH code has an error, and outputting a judgment result; and finally, outputting a high-speed parallel decoding result based on the to-be-decoded BCH code and the judgment result. According to the method, multi-bit parallel input and output data are adopted, and the error polynomial is calculated by using the iBM algorithm, so that the timeliness of the decoding process is effectively improved.

The embodiment of the invention provides an EFEC encoder, an EFEC decoder, a method, equipment and a system, and relates to the technical field of optical communication, in the EFEC encoder, a first bit width conversion module converts the bit width of input data into the bit width of an RS domain; the first control module performs blocking and value filling operation on the first RS domain data; the RS coding module performs parallel RS coding on each symbol included in the second RS domain data through a preset integer number of RS coding channels; the second control module deletes the filling value in the second RS domain data; the second bit width conversion module converts the bit width of the first RS domain data and the RS check code into the bit width of the BCH domain; the BCH coding module carries out parallel BCH coding on each symbol included in the BCH domain data through a preset integer number of BCH coding channels; and transmitting the BCH domain data and the BCH check code. According to the scheme, the encoding and decoding speed of the EFEC can be improved under the condition of saving hardware resources.

The invention relates to the technical field of signal analysis and processing, in particular to an underwater acoustic signal channel coding blind identification method and system.The method comprises the steps that firstly, preprocessed demodulation data are obtained, the data are in a bit stream form, and a threshold value is set; comparing the code word characteristics of the standard deleted convolutional code with a threshold value, and when the code word characteristics of the standard deleted convolutional code are greater than the threshold value, performing blind identification on the standard deleted convolutional code; otherwise, continuing subsequent judgment; comparing the code word characteristics of the RS code with a threshold value, and when the code word characteristics of the RS code are greater than the threshold value, performing RS code blind identification; otherwise, continuing subsequent judgment; comparing the code word characteristics of the BCH code with a threshold value, and performing BCH code blind identification when the code word characteristics of the BCH code are greater than the threshold value; otherwise, judging the coding format as an unknown coding format. According to the method, the BCH with the code length of 63 or below, the RS with the code length of 15 or below and the standard deletion convolutional codes of all code rates can be subjected to blind recognition, the requirement for the sample data size is small, and the good error code resistance performance is achieved.

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

The invention discloses a BCH code rapid identification method based on matrix transformation. The method comprises the following steps: arranging BCH code bit streams into a matrix; simplifying the bit stream matrix into an upper triangular matrix; estimating a code length and a check matrix of the BCH code according to the matrix deficit rank characteristic; estimating the generated matrix by using the orthogonality of the check matrix and the generated matrix; and simplifying the generator matrix, and estimating to obtain a generator polynomial of the BCH code. According to the method, double traversal detection does not need to be carried out on coding parameters, the timeliness of BCH code recognition can be effectively improved, and compared with an existing method, the calculation complexity is low, and BCH code online recognition can be completed in a non-cooperative confrontation environment.

The invention discloses a medium wave communication and navigation integrated signal design method. The method comprises the following steps: generating a frame synchronization code and a navigation message; segmenting a binary code of the navigation message according to a fixed bit length to obtain segmented binary codes; taking every two segmented binary codes as a group in sequence, performing serial / parallel conversion on each group of segmented binary codes, and then performing BCH error correction coding respectively; for each group of BCH codes, parallel / serial conversion is carried out according to each bit sequence to output interleaving codes, so that interleaving coding of the navigation messages is completed; and modulating and framing the navigation message and the frame synchronization code after full-hop MPPSK modulation interleaving coding to form a multi-frame signal, replacing a sine carrier in a broadcast signal with the multi-frame signal, performing composite modulation on the multi-frame signal and an analog audio signal to generate a composite modulation signal, and sending the composite modulation signal through a broadcast station. According to the invention, dual functions of broadcasting and navigation can be realized under the condition that normal use of a user is not influenced.

The invention discloses a data error correction method based on BCH coding, a storage medium and an integrated chip, and relates to the technical field of chip design and application, the data error correction method based on BCH coding comprises the following steps: obtaining target data obtained by BCH coding, and according to a target vector of the target data and a preset check matrix, correcting the target vector of the target data; determining each syndrome corresponding to the target vector; if the syndromes representing data errors exist in the determined syndromes, generating an error equation according to the syndromes; constructing a target number of verification equations based on the coefficient of the error equation, grouping the constructed verification equations, and solving each group of verification equations by adopting the same group of summation modules to obtain error position data; and performing error correction on the target data according to the error position data to obtain an error correction result. By applying the scheme provided by the embodiment of the invention, resources occupied for realizing the error correction function can be reduced.

A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a syndrome stage for generating a syndrome based on a BCH coded word, a Berlekamp-Massey stage for performing a Berlekamp-Massey (BM) algorithm on the syndrome to generate error location polynomial (ELP) coefficients, a Chien stage for performing a Chien search on the ELP coefficients using a fast Fourier transform (FFT) to generate error bits and iterative information, and a framer stage configured to reorder the error bits into an ordered frame based on the iterative information. The BCH decoder decodes the BCH coded word using the reordered error bits.

This application provides a decoder hardware architecture for concatenated RS and BCH codes, comprising a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer. The BCH decoding module and the RS decoding module employ the same target total parallelism and the same target clock frequency. This application offers the following advantages: the decoding hardware architecture enables the decoding of concatenated RS and BCH codes in ultra-high-speed communication networks of 800Gbps, 1600Gbps, and above, while simultaneously meeting the requirements of commercial applications for extremely high speed, small size, and low power consumption in decoders.

The application provides a post-processing device and method for chaotic key distribution, which comprises a driving source, a power module, a synchronous clock module, a first DFB laser, a second DFB laser, a first key control module, a second key control module, a first photoelectric detector, a second photoelectric detector, a first double-threshold quantization module, a second double-threshold quantization module, a first FPGA module and a second FPGA module. The double-threshold quantization module is used for quantizing chaotic signals, and the FPGA module is used for screening seed keys and encoding and error correction of BCH codes, so that the real-time performance and miniaturization of key distribution can be realized, and the keys generated by the two communication parties are completely consistent. The application realizes the miniaturization and high integration of the post-processing device for chaotic key distribution, has strong real-time performance, and can be applied to the field of post-processing of chaotic key distribution.

The invention belongs to the technical field of iterative decoding, and particularly relates to a soft iterative decoding method of a BCH (Broadcast Channel) code, which comprises the following steps of: for the BCH code, expanding and optimizing a standard check matrix of the BCH code to obtain a preprocessed check matrix; performing quasi-BP iterative decoding, performing expansion preprocessing on the input information based on an expansion factor, completing an iterative decoding process, and optimizing and merging weight coefficients; constructing a quasi-BP iterative decoding and ordered statistical decoding OSD hybrid decoding architecture, and when the quasi-BP iterative decoding is judged as an undetectable decoding error UDE, triggering an ordered statistical decoder OSD to perform secondary decoding; a scattered point type external information transfer graph analysis tool is introduced for parameter optimization; and carrying out soft iterative decoding on the subsequently input BCH code, and carrying out parameter optimization. According to the method, a scatter type EXIT tool is introduced to quantify and optimize parameters, the quasi-BP algorithm is universal and parallel, and high reliability, low complexity and low time delay of decoding are considered.

The invention relates to a rapid frame synchronization method, device and equipment for Beidou navigation signals and a medium, and relates to the technical field of Beidou satellite navigation. The method comprises the following steps: carrying out subframe synchronization code sliding matching on a navigation data bit stream of a Beidou navigation signal which is output by a carrier ring and is subjected to bit synchronization, and determining an initial position of a subframe of the Beidou navigation signal; the method comprises the following steps: according to an error correction coding scheme combining an interleaving technology and BCH coding adopted by a Beidou navigation signal, carrying out three times of BCH verification on the first two words of a subframe, if any one time of BCH verification is passed, then carrying out intra-week time and subframe number verification on the first two words of the subframe, and if the intra-week time and subframe number verification is passed, completing subframe synchronization of the Beidou navigation signal; otherwise, re-executing the sliding matching of the sub-frame synchronization code until the sub-frame synchronization is completed. By adopting the method, the subframe synchronization time of the Beidou navigation signal can be remarkably shortened, and the reliability and the accuracy of subframe synchronization are greatly improved.

The present invention discloses a data error correction method, storage medium, and integrated chip based on BCH coding, relating to the field of chip design and application technology. The data error correction method based on BCH coding comprises: obtaining target data obtained by BCH coding, determining each syndrome corresponding to the target vector based on the target vector of the target data and a preset check matrix; if a syndrome indicating a data error exists among the determined syndromes, generating an error equation based on each syndrome; constructing a target number of check equations based on the coefficients of the error equations, grouping the constructed check equations, and solving each group of check equations using the same set of summation modules to obtain error position data; and correcting the target data based on the error position data to obtain an error correction result. Application of the solution provided by the embodiments of the present invention can reduce the resources occupied by implementing the error correction function.

The invention belongs to the technical field of decoding, and discloses a soft input soft output decoding method for a BCH code. According to the method, the probability that a correct code word is not in a code block is accurately calculated, and rough selection of an empirical value of a scaling factor alpha in a Chase-Pyndiah decoding algorithm is replaced. Furthermore, bit-by-bit log-likelihood ratio information is obtained through probability fractional weighting operation, and the BCH code can output more reliable soft output information, so that iterative decoding can obtain certain performance gain. In addition, linear fitting is carried out on an exponential operation part with relatively high operation complexity in the algorithm, so that the hardware implementation complexity is simplified to a certain extent.