12 results about "Bch coding" patented technology

Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding / decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

The invention provides an Internet of Things data storage method and system based on a BCH code, and belongs to the technical field of data processing, and the method comprises the steps: firstly obtaining and coding an original data packet, and generating a BCH coding data block; then, constructing a storage network topology comprising a plurality of relay nodes and aggregation nodes, and pre-defining a logic association relationship for forming an incomplete connection graph structure for each relay node; distributing the data blocks to the selected part of relay nodes for storage; generating verification information fusing the storage content, the fragment identifier and the associated node information for each storage node; generating a verification path passing through at least two relay nodes based on the topology and logic association relationship; and sequentially acquiring verification information or data fragments of each node along the path, and executing chained verification on the BCH coded data block to complete integrity verification. Through the combination of coding fault tolerance, topological distributed storage and relevance chained verification, the reliability and verification efficiency of data storage of the Internet of Things are improved.

The application relates to a fast frame synchronization method, device and equipment for a Beidou navigation signal and a medium, and relates to the technical field of Beidou satellite navigation. The method comprises the following steps: performing subframe synchronization code sliding matching on a navigation data bit stream of a Beidou navigation signal output by a carrier loop and subjected to bit synchronization, and determining the starting position of a subframe of the Beidou navigation signal; performing three times of BCH checking on the first two words of the subframe according to an error correction coding scheme combining the interleaving technology and the BCH coding adopted by the Beidou navigation signal; if any time of the BCH checking is passed, then performing within-week time and subframe number checking on the first two words of the subframe; if the within-week time and subframe number checking is passed, then completing the subframe synchronization of the Beidou navigation signal; otherwise, re-executing the subframe synchronization code sliding matching until the subframe synchronization is completed. By adopting the method, the subframe synchronization time of the Beidou navigation signal can be significantly reduced, and the reliability and accuracy of the subframe synchronization can be greatly improved.

The invention belongs to the technical field of communication signal processing and code identification, and solves the problem of channel code identification when a non-cooperative communication system lacks coding parameter prior information and training data with labels. According to the technical scheme, the method is characterized in that a unified recognition framework is constructed based on five features, namely, a rank fluctuation feature is used for distinguishing convolutional codes and linear block codes, a continuous zero spectrum feature is used for recognizing BCH codes, a multi-dimensional structure feature is used for detecting Turbo product codes, a bit distribution deviation feature is used for recognizing polarization codes, and an average absolute column correlation feature is used for distinguishing LDPC codes and non-LDPC codes; blind recognition of five types of channel codes including BCH codes, LDPC codes, convolutional codes, Turbo product codes and polarization codes is achieved. The method does not depend on coding parameter prior information, does not need training, is high in recognition rate under a low signal-to-noise ratio, is high in generalization capability, and is suitable for real-time and resource-limited scenes.

Systems and methods are disclosed, including a memory system that includes a memory array and a memory controller. The memory array includes memory cells that are included in multiple memory dies. The memory controller includes a cyclic redundancy check (CRC) encoder configured to determine a CRC code using a data word received by the memory controller; and a Bose-Chaudri-Hocqenghem (BCH) encoder configured to determine a BCH code using the data word and the CRC code. The memory controller is configured to store the data word in the memory array and store the BCH code and the CRC code in the memory array in association with the data word.

This invention provides an efficient parallel encoding and decoding method for BCH codes, belonging to the technical field of BCH encoding and decoding circuit implementation in the areas of memory and error correction coding. Unlike previous lookup table methods, for an (n, k, t) BCH code with an n-bit codeword length, k data bits, and t-bit error correction capability, this invention only needs to store the values ​​of k n-k bit parity check matrix column vectors. These k n-k bit parity check matrix column vectors are then XORed with the S-synonym value for t rounds. The error pattern corresponding to the received codeword is obtained from the bitwise XOR value and corrected. This invention is a hardware-level encoding and decoding implementation, which can be completed within one clock cycle, reducing the multi-cycle decoding delay caused by iterative algorithms, achieving parallelization of BCH encoding and decoding, simplifying the encoding and decoding process, and reducing resource consumption.

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

The application provides a post-processing device and method for chaotic key distribution, which comprises a driving source, a power module, a synchronous clock module, a first DFB laser, a second DFB laser, a first key control module, a second key control module, a first photoelectric detector, a second photoelectric detector, a first double-threshold quantization module, a second double-threshold quantization module, a first FPGA module and a second FPGA module. The double-threshold quantization module is used for quantizing chaotic signals, and the FPGA module is used for screening seed keys and encoding and error correction of BCH codes, so that the real-time performance and miniaturization of key distribution can be realized, and the keys generated by the two communication parties are completely consistent. The application realizes the miniaturization and high integration of the post-processing device for chaotic key distribution, has strong real-time performance, and can be applied to the field of post-processing of chaotic key distribution.

The invention belongs to the technical field of iterative decoding, and particularly relates to a soft iterative decoding method of a BCH (Broadcast Channel) code, which comprises the following steps of: for the BCH code, expanding and optimizing a standard check matrix of the BCH code to obtain a preprocessed check matrix; performing quasi-BP iterative decoding, performing expansion preprocessing on the input information based on an expansion factor, completing an iterative decoding process, and optimizing and merging weight coefficients; constructing a quasi-BP iterative decoding and ordered statistical decoding OSD hybrid decoding architecture, and when the quasi-BP iterative decoding is judged as an undetectable decoding error UDE, triggering an ordered statistical decoder OSD to perform secondary decoding; a scattered point type external information transfer graph analysis tool is introduced for parameter optimization; and carrying out soft iterative decoding on the subsequently input BCH code, and carrying out parameter optimization. According to the method, a scatter type EXIT tool is introduced to quantify and optimize parameters, the quasi-BP algorithm is universal and parallel, and high reliability, low complexity and low time delay of decoding are considered.

The invention belongs to the technical field of decoding, and discloses a soft input soft output decoding method for a BCH code. According to the method, the probability that a correct code word is not in a code block is accurately calculated, and rough selection of an empirical value of a scaling factor alpha in a Chase-Pyndiah decoding algorithm is replaced. Furthermore, bit-by-bit log-likelihood ratio information is obtained through probability fractional weighting operation, and the BCH code can output more reliable soft output information, so that iterative decoding can obtain certain performance gain. In addition, linear fitting is carried out on an exponential operation part with relatively high operation complexity in the algorithm, so that the hardware implementation complexity is simplified to a certain extent.

The invention relates to the field of wireless communication networks, and provides a BCH (Broadcast Channel) code parallel decoding method based on artificial intelligence, which comprises the following steps of: acquiring a to-be-decoded BCH receiving code word from a physical channel; inputting a to-be-decoded BCH receiving code word into the trained error pattern prediction model, outputting a predicted error pattern, and performing error correction on the to-be-decoded BCH receiving code word by using the predicted error pattern to obtain an estimated sending code word; respectively carrying out syndrome calculation on the BCH receiving code word to be decoded and the estimated sending code word so as to judge the validity of the code word; and based on a result of syndrome calculation, carrying out dual-channel decoding control according to a sequence of firstly judging a BCH receiving code word to be decoded and then judging an estimated sending code word, carrying out parallel prediction on an error pattern of the BCH receiving code word by introducing an artificial intelligence model, bypassing a serial iterative calculation bottleneck in a traditional BCH decoding process, and carrying out decoding on the error pattern of the BCH receiving code word. Error position determination can be completed in a single forward reasoning process, decoding time delay is effectively reduced, and throughput is improved.

The invention discloses a non-aligned BCH codeword syndrome calculation implementation method, and belongs to the technical field of communication. The method comprises the following steps: a sending end performs coding transmission on data by adopting a BCH code; the receiving end receives the coded code word from the channel; performing syndrome calculation on the received code word to judge whether an error code occurs or not; judging according to the head and tail position conditions of non-aligned code words in the received code words; if the first bit of the current code word is located at the aligned position, adopting a syndrome iterative calculation mode of the aligned position; and if the first position of the received code word is not aligned, calculating an intermediate process value of the improved syndrome iteration by adopting an improved syndrome iterative calculation mode, and updating the syndrome iteration according to the intermediate process value to obtain a final output result of the code word which is calculated by adopting the improved syndrome iterative calculation. According to the method disclosed by the invention, the syndrome parallel computing processing on the non-aligned BCH code word is realized by improving the syndrome computing mode under the condition of not shifting data.