Fast frame synchronization method, device and equipment for beidou navigation signal and medium

Abstract

The application relates to a fast frame synchronization method, device and equipment for a Beidou navigation signal and a medium, and relates to the technical field of Beidou satellite navigation. The method comprises the following steps: performing subframe synchronization code sliding matching on a navigation data bit stream of a Beidou navigation signal output by a carrier loop and subjected to bit synchronization, and determining the starting position of a subframe of the Beidou navigation signal; performing three times of BCH checking on the first two words of the subframe according to an error correction coding scheme combining the interleaving technology and the BCH coding adopted by the Beidou navigation signal; if any time of the BCH checking is passed, then performing within-week time and subframe number checking on the first two words of the subframe; if the within-week time and subframe number checking is passed, then completing the subframe synchronization of the Beidou navigation signal; otherwise, re-executing the subframe synchronization code sliding matching until the subframe synchronization is completed. By adopting the method, the subframe synchronization time of the Beidou navigation signal can be significantly reduced, and the reliability and accuracy of the subframe synchronization can be greatly improved.

Description

Technical Field

[0001] This application relates to the field of BeiDou satellite navigation technology, and in particular to a fast frame synchronization method, apparatus, device and medium for BeiDou navigation signals. Background Technology

[0002] In practical applications, the BeiDou Navigation Satellite System faces a technical bottleneck when receivers are in a cold-start state: excessively long subframe synchronization times significantly increase the initial positioning time, directly impacting the efficiency of navigation information acquisition and system response speed. This is particularly problematic in time-sensitive applications such as UAV navigation, emergency rescue, and intelligent transportation, where prolonged subframe synchronization can cause navigation service delays, thereby affecting system availability and reliability. Therefore, shortening the initial positioning time is crucial for enhancing the competitiveness of the BeiDou Navigation Satellite System.

[0003] Existing BeiDou navigation signal subframe synchronization methods acquire the synchronization code by performing bit-by-bit correlation operations between the navigation data bitstream output from the carrier loop and the subframe synchronization code. Due to the 180° phase ambiguity in the carrier tracking loop, the start position of the subframe can be preliminarily determined when the synchronization code or its inverse code (i.e., the phase-reversed synchronization code) is detected during correlation detection. To ensure the reliability of frame synchronization, the system needs to perform a secondary check 300 navigation data bits (i.e., the length of a complete subframe) after the subframe start position. If the subframe synchronization code or its inverse code is detected again at this position, successful subframe synchronization can be confirmed. However, this method has a significant limitation: it requires receiving at least one subframe plus a frame header (311 bits in total) to complete subframe synchronization, resulting in an excessively long frame synchronization time. This is particularly problematic under cold-start conditions, severely impacting the initial positioning time of the navigation receiver. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, device, and medium for fast frame synchronization of BeiDou navigation signals to address the aforementioned technical problems.

[0005] A fast frame synchronization method for BeiDou navigation signals, the method comprising:

[0006] Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal.

[0007] Step 2: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to Step 3; otherwise, return to Step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0008] Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0009] In one embodiment, subframe synchronization code sliding matching is performed on the navigation data bitstream of the BeiDou navigation signal output from the carrier loop and after bit synchronization to determine the start position of the subframe of the BeiDou navigation signal, including:

[0010] Using a predefined 11-bit subframe synchronization code as a sliding window, continuous subframe synchronization code sliding matching is performed on the navigation data bitstream of the BeiDou navigation signal output from the carrier loop and after bit synchronization, until a correlation peak satisfying the synchronization criterion is detected, thereby achieving accurate acquisition of the subframe start position of the BeiDou navigation signal; wherein, the correlation function of the subframe synchronization code sliding matching is expressed as:

[0011] ;

[0012] Where k is the length of the sliding window, used to ensure that the received navigation data bitstream sequence... Find the subframe synchronization code, where k takes the value 311; Indicates the subframe synchronization code sequence. and All are represented in bipolar form, that is, bit 0 is mapped to +1 and bit 1 is mapped to -1; This is the index of the subframe synchronization code sequence;

[0013] When the navigation data bitstream sequence within the sliding window perfectly matches the subframe synchronization code sequence, all corresponding bit symbols are consistent, and the output of the correlation function is... The maximum value is reached +11; the output of the correlation function is when the navigation data bitstream sequence within the sliding window completely matches the subframe synchronization inverted code sequence. The minimum value of -11 is reached, therefore the criterion for determining successful subframe synchronization detection is defined as follows: .

[0014] In one embodiment, based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, the first two words of the subframe are subjected to three BCH checks, including:

[0015] According to the first word of each subframe of the Beidou navigation signal, the first 15 bits of navigation information contain the subframe synchronization code without a coding scheme, and the last 11 bits of navigation information adopt the BCH(15,11,1) coding scheme. The last 15 bits of navigation information of the first word of the subframe are subjected to BCH(15,11,1) check decoding.

[0016] According to the error correction coding scheme that combines interleaving technology and BCH(15,11,1) coding for the remaining 30 bits of each subframe of the Beidou navigation signal, the 30 bits of the second word of the subframe are first deinterleaved to obtain the 30-bit serial input data. Then, the serial-to-parallel conversion is performed according to the order of each bit to separate the navigation information into two groups of 15 bits each. Each group is then subjected to BCH(15,11,1) check decoding.

[0017] In one embodiment, the error correction coding scheme consists of an 11-bit information code and a 4-bit check code, whose generator polynomial is... for:

[0018] ;

[0019] in, Represents the first in a binary codeword Position and Its coefficient is 0 or 1.

[0020] In one embodiment, BCH(15,11,1) checksum decoding includes:

[0021] First, the shift register is initialized and cleared. Then, the received 15-bit BCH encoded sequence is input bit by bit into the polynomial division circuit and the 15-stage error correction buffer. After all the codewords of the 15-bit BCH encoded sequence have been input, the current state D0 to D3 of the 4-bit shift register in the polynomial division circuit (i.e., the syndrome) is used as the address index, and the corresponding 15-bit error correction signal is obtained by querying the pre-stored error correction signal ROM table. Modulo-2 addition is performed on the 15-bit error correction signal and the received codewords in the 15-stage error correction buffer to output the corrected error correction decoder.

[0022] When the syntactic expression D3D2D1D0 is 0000, it indicates that there are no errors in the BCH check and the BCH check is considered to have passed; otherwise, the BCH check is considered to have failed.

[0023] In one embodiment, the first two words of the subframe are checked for week-time and subframe number, including:

[0024] The subframe ID identifier is obtained from bits 16 to 18 of the first word of the subframe of the BeiDou navigation signal. The weektime information, a total of 20 bits, is obtained from bits 19 to 26 of the first word and bits 1 to 12 of the second word of the subframe. The subframe ID identifier and the weektime information are checked to see if they meet the preset value range. The subframe synchronization is considered successful only if both meet the preset value range. Otherwise, the subframe synchronization is considered unsuccessful, and the process returns to step 1 to re-execute the subframe synchronization code sliding matching. The subframe ID identifier has a value range of 1 to 5, and the weektime information has a value range of 0 to 604799 seconds.

[0025] A fast frame synchronization device for BeiDou navigation signals, the device comprising:

[0026] The subframe synchronization code sliding matching module is used to perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization, to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal;

[0027] The BCH verification module is used to perform three BCH verifications on the first two words of a subframe based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals. If any BCH verification passes, it enters the weektime and subframe number verification module; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching. The three BCH verifications include one BCH verification on the navigation information of the first word, and one BCH verification on the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0028] The weektime and subframe number verification module is used to verify the weektime and subframe number of the first two characters of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0029] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program performing the following steps:

[0030] Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal.

[0031] Step 2: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to Step 3; otherwise, return to Step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0032] Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0033] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0034] Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal.

[0035] Step 2: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to Step 3; otherwise, return to Step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0036] Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0037] The aforementioned fast frame synchronization method, apparatus, equipment, and medium for BeiDou navigation signals, after determining the starting position of a subframe by searching and matching the subframe synchronization code, innovatively introduces a BCH verification mechanism into the subframe synchronization process. This mechanism is tailored to the error correction coding scheme that combines the unique interleaving technology and BCH coding of BeiDou B1I and BeiDou B3I signals. Instead of receiving the next complete subframe data, it directly performs three BCH verifications on the first two words of the subframe. This reduces the minimum data reception time for traditional subframe synchronization from 311 bits to 60 bits (the first two words of the subframe) without relying on external information or changing the original message format. This significantly shortens the subframe synchronization time of BeiDou navigation signals, thereby significantly improving the subframe synchronization speed and first positioning time of the BeiDou navigation receiver under cold start conditions. Furthermore, based on the BCH verification, a triple verification mechanism is constructed by introducing weektime and subframe number dual verifications. This significantly reduces the subframe synchronization time while greatly improving the reliability and accuracy of subframe synchronization, enhancing the availability and competitiveness of the BeiDou navigation system in highly dynamic and time-sensitive scenarios. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating a fast frame synchronization method for BeiDou navigation signals in one embodiment;

[0039] Figure 2 This is a schematic diagram of the D1 navigation message frame structure in one embodiment;

[0040] Figure 3 This is a schematic diagram of an error correction coding structure that combines interleaving technology and BCH coding in one embodiment of the D1 navigation message;

[0041] Figure 4 This is a schematic diagram of the BCH(15,11,1) check decoding process in one embodiment.

[0042] Figure 5 This is a schematic diagram of the subframe structure of BeiDou navigation signals in one embodiment;

[0043] Figure 6 A comparison diagram of the synchronization time of B3I signal subframes between the traditional method and the method proposed in this application;

[0044] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] It should be understood that due to the 180° phase ambiguity in the carrier loop, navigation information bits may be completely out of phase. Therefore, the subframe synchronization process must search for both sequences matching the subframe synchronization code and sequences that are out of phase with it. The occurrence of data bits 0 and 1 in the navigation message is random. The probability that 11 randomly generated consecutive bits are exactly the synchronization code and its inverse code is:

[0047] ;

[0048] The probability that any 11 consecutive bits will be mistaken for a synchronization code or its inverse code is:

[0049] ;

[0050] For continuous navigation signals, the probability is not small, so after finding the synchronization code or its inverse code in the bit stream, further confirmation is needed to ensure the reliability of subframe synchronization.

[0051] Traditional subframe synchronization methods determine successful frame synchronization by matching the subframe synchronization code twice consecutively, which is time-consuming. This application proposes a fast frame synchronization method for BeiDou navigation signals. After matching the subframe synchronization code, it performs three BCH checks on the first two words of the subframe, as well as checks on the weektime and subframe number, to ensure that the matched subframe synchronization code is the true synchronization code, significantly reducing frame synchronization time. Figure 1 As shown, the method proposed in this application includes the following steps:

[0052] Step 1, Match subframe synchronization codes to determine the starting position of subframes: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframes of the BeiDou navigation signal.

[0053] The BeiDou navigation signal includes BeiDou B1I and BeiDou B3I signals. Its navigation messages are divided into two types: D1 and D2. Their message structures are basically the same, but the subframe broadcast durations differ. Taking the D1 navigation message as an example, its message frame structure is as follows: Figure 2As shown, the system consists of superframes, main frames, subframes, and words. Each superframe is 36,000 bits long, composed of 24 main frames, and has a broadcast duration of 12 minutes. Each main frame is 1,500 bits long, composed of 5 subframes, and has a broadcast duration of 30 seconds. Each subframe is 300 bits long, composed of 10 words, and has a broadcast duration of 6 seconds. Each word is 30 bits long, consisting of navigation message information and its check code, and has a broadcast duration of 0.6 seconds. The first 11 bits of the first word in each subframe are fixed and constitute the subframe synchronization code, which consists of an 11-bit modified Barker code with a value of 11100010010. The first word of each subframe is not interleaved, the first 15 bits of information are not error-correcting encoded, and the last 11 bits of information adopt the BCH(15,11,1) encoding scheme. The navigation message information bits of the first word have a total of 26 bits, and the check code is 4 bits. The other 9 words adopt an error-correcting encoding scheme that combines interleaving technology with BCH(15,11,1) encoding. The navigation message information bits have a total of 22 bits, and the check code is 8 bits.

[0054] Step 1 specifically includes: using a predefined 11-bit subframe synchronization code (11100010010) as a sliding window, continuously performing subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output from the carrier ring and after bit synchronization, until a correlation peak satisfying the synchronization criterion is detected, thus achieving accurate acquisition of the subframe start position of the BeiDou navigation signal. This navigation data bit search and matching process can be considered a discrete correlation operation, and the correlation function of the subframe synchronization code sliding matching is expressed as:

[0055] ;

[0056] Where k is the length of the sliding window, used to ensure that the received navigation data bitstream sequence... Find the subframe synchronization code, where k takes the value 311; Indicates the subframe synchronization code sequence. and All are represented in bipolar form, that is, bit 0 is mapped to +1 and bit 1 is mapped to -1; This is the index of the subframe synchronization code sequence.

[0057] When the navigation data bitstream sequence within the sliding window perfectly matches the subframe synchronization code sequence, all corresponding bit symbols are consistent, and the output of the correlation function is... The maximum value is reached +11; the output of the correlation function is when the navigation data bitstream sequence within the sliding window completely matches the subframe synchronization inverted code sequence. The minimum value of -11 is reached, therefore the criterion for determining successful subframe synchronization detection is defined as follows: .

[0058] Step 2: Perform three BCH checks on the first two words of the received subframe: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to step 3; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0059] Step 2 specifically includes:

[0060] According to the first word of each subframe of the BeiDou navigation signal, the first 15 bits of navigation information contain the subframe synchronization code without a coding scheme, and the last 11 bits of navigation information adopt the BCH(15,11,1) coding scheme. The last 15 bits of navigation information of the first word of the subframe are subjected to BCH(15,11,1) check decoding.

[0061] According to the error correction coding scheme that combines interleaving technology and BCH(15,11,1) coding for the remaining 30 bits of each subframe of the Beidou navigation signal, the 30 bits of the second word of the subframe are first deinterleaved to obtain the 30-bit serial input data. Then, the serial-to-parallel conversion is performed according to the order of each bit to separate the navigation information into two groups of 15 bits each. Each group is then subjected to BCH(15,11,1) check decoding.

[0062] Specifically, the 2nd to 10th words of each subframe of the BeiDou B1I and BeiDou B3I signals are combined into a 30-bit word using an error correction coding scheme that combines interleaving technology with BCH(15,11,1) coding. This scheme enables the combination of two adjacent groups of navigation information encoded by BCH(15,11,1) into a 30-bit word, thus providing 1-bit error correction capability. The error correction coding scheme consists of 11 bits of information code and 4 bits of check code, and its generator polynomial is... for:

[0063] ;

[0064] in, Represents the first in a binary codeword Position and Its coefficient is either 0 or 1. The error correction coding structure is as follows: Figure 3 As shown, Figure 3 middle Representing the i The first group of BCH codes j Information bits ( j The value range is 1 to 11. Indicates the first i The first group of BCH codes k One check bit ( k The value range is 1 to 4.

[0065] Table 1 Error Correction Signal ROM Table

[0066]

[0067] The BCH(15,11,1) checksum decoding process is as follows: Figure 4 As shown, the process includes: first, initializing and clearing the shift register; then, inputting the received 15-bit BCH encoded sequence bit by bit into the polynomial division circuit and the 15-stage error correction buffer; after all the codewords of the 15-bit BCH encoded sequence have been input, using the current state D0 to D3 of the 4-bit shift register in the polynomial division circuit (i.e., the syndrome) as the address index, and querying the pre-stored error correction signal ROM table as shown in Table 1, to obtain the corresponding 15-bit error correction signal; performing a modulo-2 addition operation on the 15-bit error correction signal and the received codewords in the 15-stage error correction buffer, and outputting the corrected error-corrected decoder; where, when the syndrome D3D2D1D0 is 0000, it indicates that there are no errors in the BCH check, and the BCH check is determined to be successful; otherwise, the BCH check is determined to be unsuccessful. In this application, after matching the subframe synchronization code, three BCH checks are performed on the data bits of two consecutive received words. If at least one of the three BCH checks yields a symptom D3D2D1D0 of 0000, the BCH check is considered successful; otherwise, the process returns to step 1 to rematch the subframe synchronization code. The false positive probability after three BCH checks is reduced by an order of magnitude compared to before the checks, significantly improving the reliability of frame synchronization.

[0068] Step 3: Perform weektime and subframe number verification on the first two words of the subframe: If the weektime and subframe number verification passes, complete the subframe synchronization of the BeiDou navigation signal; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0069] Step 3 specifically includes: Figure 5In the subframe structure of the BeiDou navigation signal shown, specific bits in the first two characters carry key navigation information parameters: the subframe ID is obtained from bits 16 to 18 of the first character of the BeiDou navigation signal subframe, and 20 bits of weektime time information are obtained from bits 19 to 26 of the first character and bits 1 to 12 of the second character. The subframe ID and weektime time information are checked against preset value ranges. Subframe synchronization is considered successful only if both meet the preset ranges; otherwise, subframe synchronization is considered unsuccessful, and the process returns to step 1 to re-execute the subframe synchronization code sliding match. This dual-check mechanism can reduce the probability of subframe synchronization errors to an extremely low level. The subframe ID ranges from 1 to 5, and the weektime time information ranges from 0 to 604799 seconds. Figure 5 In this context, MSB and LSB represent the most significant bit and the least significant bit, respectively.

[0070] In summary, the fast frame synchronization method for BeiDou navigation signals provided in this application, through searching a frame header and performing a triple verification mechanism on the first two words of the subframe, including three BCH checks, weektime time checks, and subframe number checks, reduces the minimum subframe synchronization time from the traditional 6.22s to 1.2s for B1I and B3I signals using D1 navigation messages, while ensuring subframe synchronization reliability. The time consumed by BCH checks, weektime time checks, and subframe number checks is in the millisecond range and can be ignored. This method significantly shortens the subframe synchronization time of BeiDou navigation signals, thereby reducing the cold start time of BeiDou navigation receivers. Furthermore, it significantly improves the reliability and accuracy of subframe synchronization while significantly reducing the synchronization time, enhancing the availability and competitiveness of the BeiDou navigation system in high-dynamic and time-sensitive scenarios.

[0071] To verify the beneficial performance of the proposed method, multiple comparative experiments were conducted on subframe synchronization of B3I signals compared with traditional methods. The results are as follows: Figure 6 As shown, the subframe synchronization time of the method proposed in this application is significantly better than that of the traditional method in every experiment.

[0072] In one embodiment, a fast frame synchronization device for BeiDou navigation signals is provided, comprising:

[0073] The subframe synchronization code sliding matching module is used to perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization, to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal;

[0074] The BCH verification module is used to perform three BCH verifications on the first two words of a subframe based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals. If any BCH verification passes, it enters the weektime and subframe number verification module; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching. The three BCH verifications include one BCH verification on the navigation information of the first word, and one BCH verification on the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0075] The weektime and subframe number verification module is used to verify the weektime and subframe number of the first two characters of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0076] Specific limitations regarding the fast frame synchronization device for BeiDou navigation signals can be found in the limitations of the fast frame synchronization method for BeiDou navigation signals described above, and will not be repeated here. Each module in the aforementioned fast frame synchronization device for BeiDou navigation signals can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0077] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a fast frame synchronization method for BeiDou navigation signals. The display screen can be an LCD screen or an e-ink display screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0078] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0079] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to perform the following steps:

[0080] Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal.

[0081] Step 2: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to Step 3; otherwise, return to Step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0082] Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0083] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0084] Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes the BeiDou B1I signal and the BeiDou B3I signal.

[0085] Step 2: Based on the error correction coding scheme that combines interleaving technology and BCH coding used in BeiDou navigation signals, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to Step 3; otherwise, return to Step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word.

[0086] Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

[0087] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0088] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A fast frame synchronization method for BeiDou navigation signals, characterized in that, The method includes: Step 1: Perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes BeiDou B1I signal and BeiDou B3I signal. Step 2: According to the error correction coding scheme that combines interleaving technology and BCH coding used in the BeiDou navigation signal, perform three BCH checks on the first two words of the subframe. If any BCH check passes, proceed to step 3; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching. The three BCH checks include performing one BCH check on the navigation information of the first word, and performing one BCH check on each of the two sets of navigation information obtained after deinterleaving and serial-to-parallel conversion of the second word. Step 3: Perform weektime and subframe number verification on the first two words of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, return to step 1 and re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

2. The fast frame synchronization method for BeiDou navigation signals according to claim 1, characterized in that, Subframe synchronization code sliding matching is performed on the navigation data bitstream of the BeiDou navigation signal output from the carrier loop and after bit synchronization to determine the start position of the subframe of the BeiDou navigation signal, including: Using a predefined 11-bit subframe synchronization code as a sliding window, continuous subframe synchronization code sliding matching is performed on the navigation data bitstream of the BeiDou navigation signal output from the carrier ring and after bit synchronization, until a correlation peak satisfying the synchronization criterion is detected, thereby achieving accurate acquisition of the subframe start position of the BeiDou navigation signal; wherein, the correlation function of the subframe synchronization code sliding matching is expressed as: ； Where k is the length of the sliding window, used to ensure that the received navigation data bitstream sequence... Find the subframe synchronization code, where k takes the value 311; Indicates the subframe synchronization code sequence. and They are all represented in bipolar form, that is, bit 0 is mapped to +1 and bit 1 is mapped to -1; This is the index of the subframe synchronization code sequence; When the navigation data bitstream sequence within the sliding window perfectly matches the subframe synchronization code sequence, all corresponding bit symbols are consistent, and the output of the correlation function is... The maximum value is reached +11; the output of the correlation function is when the navigation data bitstream sequence within the sliding window completely matches the subframe synchronization inverted code sequence. The minimum value of -11 is reached, therefore the criterion for determining successful subframe synchronization detection is defined as follows: .

3. The fast frame synchronization method for BeiDou navigation signals according to claim 1, characterized in that, Based on the error correction coding scheme combining interleaving technology and BCH coding used in the BeiDou navigation signal, the first two words of the subframe undergo three BCH checks, including: According to the first word of each subframe of the Beidou navigation signal, the first 15 bits of navigation information contain a subframe synchronization code without a coding scheme, and the last 11 bits of navigation information adopt the BCH(15,11,1) coding scheme. The last 15 bits of navigation information of the first word of the subframe are subjected to BCH(15,11,1) check decoding. According to the error correction coding scheme that combines interleaving technology and BCH(15,11,1) coding for the remaining 30 bits of each subframe of the Beidou navigation signal, the 30 bits of the second word of the subframe are first deinterleaved to obtain 30 bits of serial input data. Then, serial-to-parallel conversion is performed according to the order of each bit to separate two groups of 15 bits of navigation information. Each group is then subjected to BCH(15,11,1) check decoding.

4. The fast frame synchronization method for BeiDou navigation signals according to claim 3, characterized in that, The error correction coding scheme consists of 11 bits of information code and 4 bits of check code, and its generator polynomial is... for: ； in, Represents the first in a binary codeword Position and Its coefficient is 0 or 1.

5. The fast frame synchronization method for BeiDou navigation signals according to claim 3, characterized in that, The BCH(15,11,1) checksum decoding includes: First, the shift register is initialized and cleared. Then, the received 15-bit BCH encoded sequence is input bit by bit into the polynomial division circuit and the 15-stage error correction buffer. After all the codewords of the 15-bit BCH encoded sequence have been input, the current states D0 to D3 of the 4-bit shift register in the polynomial division circuit (i.e., the syndrome) are used as address indices. The corresponding 15-bit error correction signal is obtained by querying the pre-stored error correction signal ROM table. Modulo-2 addition is performed on the 15-bit error correction signal and the received codewords in the 15-stage error correction buffer to output the corrected error correction decoder. When the syntactic expression D3D2D1D0 is 0000, it indicates that there are no errors in the BCH check and the BCH check is considered to have passed; otherwise, the BCH check is considered to have failed.

6. The fast frame synchronization method for BeiDou navigation signals according to claim 1, characterized in that, Perform week-time and subframe number checks on the first two words of the subframe, including: The subframe ID identifier is obtained from bits 16 to 18 of the first word of the subframe of the BeiDou navigation signal, and 20 bits of weektime time information are obtained from bits 19 to 26 of the first word and bits 1 to 12 of the second word of the subframe. The subframe ID identifier and the weektime time information are checked to see if they meet the preset value range. If both meet the preset value range, the subframe synchronization is determined to be successful; otherwise, the subframe synchronization is determined to be unsuccessful, and the process returns to step 1 to re-execute the subframe synchronization code sliding matching. The subframe ID identifier has a value range of 1 to 5, and the weektime time information has a value range of 0 to 604799 seconds.

7. A fast frame synchronization device for BeiDou navigation signals, characterized in that, The device includes: The subframe synchronization code sliding matching module is used to perform subframe synchronization code sliding matching on the navigation data bit stream of the BeiDou navigation signal output by the carrier ring and after bit synchronization, to determine the starting position of the subframe of the BeiDou navigation signal; the BeiDou navigation signal includes BeiDou B1I signal and BeiDou B3I signal. The BCH verification module is used to perform three BCH verifications on the first two words of a subframe according to the error correction coding scheme that combines interleaving technology and BCH coding adopted by the BeiDou navigation signal. If any BCH verification passes, it enters the weektime and subframe number verification module; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching. The three BCH verifications include performing one BCH verification on the navigation information of the first word, and performing one BCH verification on each of the two sets of navigation information obtained by deinterleaving and serial-to-parallel conversion of the second word. The weektime and subframe number verification module is used to verify the weektime and subframe number of the first two characters of the subframe. If the verification passes, the subframe synchronization of the BeiDou navigation signal is completed; otherwise, it returns to the subframe synchronization code sliding matching module to re-execute the subframe synchronization code sliding matching until the subframe synchronization is completed.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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