Encoder device and method for short code length multi-system weighted repeat-accumulate code

Abstract

The invention discloses an encoder device for a short code length multi-system weighted repeat-accumulate code. The device comprises an input information symbol cache unit, a coding arithmetic unit and an output code symbol cache unit which are connected with a control circuit respectively, the control circuit comprises an input control counter, a master control counter and an output control counter which are sequentially connected, a counting signal a output by the master control counter is connected with logic and gate though a counting comparator, a gate signal g output by the master control counter is respectively connected with the logic and gate and the output code symbol cache unit, output of the logic and gate is connected with the input information symbol cache unit and the coding arithmetic unit, output of the output control counter is connected with the output code symbol cache unit, the coding arithmetic unit comprises a weighted repeat-accumulate arithmetic unit, a weighted accumulating unit and a selector which are sequentially connected, and the selector is directly connected with a signal input end of the coding arithmetic unit. According to the encoder device for the short code length multi-system weighted repeat-accumulate code, the complexity and coding delay have a linear relation with the code length, the achieving mode is simple, and the device is convenient to apply to the communication system.

Description

technical field

[0001] The invention relates to an encoder device. In particular, it relates to an encoder device and method for short-code-length multi-ary weighted repetition-accumulation codes with low encoding complexity and storage unit requirements. Background technique

[0002] In modern digital signal transmission and storage systems, due to transmission channel noise or physical damage to storage media, digital signal transmission or storage errors are often caused. Therefore, in order to ensure the reliability of digital signal transmission or storage, error control coding technology has become a standard technique.

[0003] Low-Density Parity-Check (LDPC) code is an error control coding technology with superior performance. It was first proposed by Gallager in 1962. For a long time, LDPC codes have not been paid attention to and promoted. Until 1996, when D.MacKay and R.Neal rediscovered LDPC codes and proved that they had good error correction performance, LDP...

Examples

specific Embodiment

[0095] The encoder device proposed by the present invention can be realized by using Field Programmable Gate Array (Field Programmable Gate Array, FPGA). Instructions attached figure 2 The dual-port random access memory (Random Access Memory, RAM) module and attached image 3 The RAM module in can adopt the RAM module integrated in FPGA chip to realize. attached figure 2 And attached image 3 The multi-ary weight coefficient storage array and non-zero element position storage array in Figure 4 The storage array of non-zero element positions inside the gating network, and the attached Figure 5 And attached Figure 6 The multiplier coefficient memory in the FPGA chip can be implemented by a read-only memory (Read-Only Memory, ROM) module integrated in the FPGA chip.

[0096] If an independent RAM module and ROM module are used to realize the encoder device proposed in this patent, the attached figure 2 The dual-port RAM module can be realized by the dual-port RAM chi...

technical field

[0001] The invention relates to an encoder device. In particular, it relates to an encoder device and method for short-code-length multi-ary weighted repetition-accumulation codes with low encoding complexity and storage unit requirements. Background technique

[0002] In modern digital signal transmission and storage systems, due to transmission channel noise or physical damage to storage media, digital signal transmission or storage errors are often caused. Therefore, in order to ensure the reliability of digital signal transmission or storage, error control coding technology has become a standard technique.

[0003] Low-Density Parity-Check (LDPC) code is an error control coding technology with superior performance. It was first proposed by Gallager in 1962. For a long time, LDPC codes have not been paid attention to and promoted. Until 1996, when D.MacKay and R.Neal rediscovered LDPC codes and proved that they had good error correction performance, LDP...

Examples

specific Embodiment

[0095] The encoder device proposed by the present invention can be realized by using Field Programmable Gate Array (Field Programmable Gate Array, FPGA). Instructions attached figure 2 The dual-port random access memory (Random Access Memory, RAM) module and attached image 3 The RAM module in can adopt the RAM module integrated in FPGA chip to realize. attached figure 2 And attached image 3 The multi-ary weight coefficient storage array and non-zero element position storage array in Figure 4 The storage array of non-zero element positions inside the gating network, and the attached Figure 5 And attached Figure 6 The multiplier coefficient memory in the FPGA chip can be implemented by a read-only memory (Read-Only Memory, ROM) module integrated in the FPGA chip.

[0096] If an independent RAM module and ROM module are used to realize the encoder device proposed in this patent, the attached figure 2 The dual-port RAM module can be realized by the dual-port RAM chi...

Images