9 results about "Error control coding" patented technology

The invention discloses a power bank with a data storage function and an electromagnetic interference suppression method thereof, and the method comprises the steps: obtaining the operation parameters of a wireless charging coil and the operation indexes of a high-speed data link, and carrying out the segmentation statistics and time-frequency correlation matching processing, thereby obtaining an interference characteristic parameter set; performing spread spectrum migration and duty ratio-phase joint modulation on the coil driving signal; executing cache rearrangement and time sequence revision on the to-be-sent data frame; carrying out adaptive adjustment on the error control coding parameter according to the interference intensity value; and performing comprehensive optimization processing on each parameter set to generate an updated control parameter set, and forming a closed-loop control system. According to the technical scheme, under the condition that hardware shielding is not increased, fine cooperative control over the charging magnetic field and data transmission can be achieved through a software algorithm, electromagnetic interference is effectively restrained, wireless charging and high-speed data transmission can be stably and parallelly operated under the condition that space is limited, and the reliability of data transmission and the overall user experience are improved.

The invention discloses a self-adaptive modulation method and device for a power line carrier communication system, which belongs to the technical field of power line carrier communication, and comprises the following steps of: acquiring channel information of the power line carrier communication system, including a transmission characteristic value of each sub-channel and the total transmitting power of the system, and calculating the signal-to-noise ratio of each sub-channel; according to the signal-to-noise ratio of each sub-channel and the total transmission power of the system, calculating the power value allocated to each sub-channel, adjusting the original power peak-to-average ratio of the sub-channel, determining the adjusted power peak-to-average ratio, and calculating the adjusted coding gain through an optimization coefficient related to the system characteristics in combination with the adjusted power peak-to-average ratio and the original coding gain; according to the method, the performance and the reliability of the power line carrier communication system are improved by reasonably distributing the sub-channel power, controlling the peak-to-average power ratio, optimizing the error control coding gain and intelligently switching the working mode.

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

The present invention discloses a highly reliable and secure transmission method based on OTFS. For a source sequence at the transmitting end, a transmission sequence is obtained after sequentially undergoing LDPC encoding, QAM mapping, SVD precoding, inverse symplectic finite Fourier transform, Heisenberg transform, R-CP addition, D / A conversion, and up-conversion, which is then transmitted via a wireless channel. After a legitimate user's receiving end obtains the received sequence, down-conversion, A / D conversion, R-CP removal, Wigner transform, symplectic finite Fourier transform, SVD decoding, single-tap equalizer processing, QAM demapping, and LDPC decoding are performed to obtain a destination sequence. The present invention achieves highly reliable physical layer secure transmission in highly dynamic communication scenarios through precoding technology based on an OTFS equivalent matrix and error control coding technology based on LDPC, thereby improving system total throughput and spectrum efficiency, and reducing system peak-to-average ratio and transmission bit error rate, while simultaneously avoiding excessive computational complexity and time-frequency resource overhead.

The invention discloses a polarization code belief propagation decoding method for correcting insertion and deletion errors, and relates to the field of digital communication error control coding. The method comprises the following steps: mixing information bits with the length of 1 and all-zero frozen bits with the length of 1 according to position indexes of preset information bits and fixed bits to obtain a bit sequence; encoding the bit sequence to obtain a sending sequence with the length of 1; the sending sequence is transmitted through an IDS channel to obtain a receiving sequence with the length of the IDS channel; and carrying out insertion and deletion error correction processing on the receiving sequence through a BP decoder based on a weighted Lelwstein distance, and outputting an information sequence estimated value. According to the method, the drift distance is introduced, and the weighted Levinstein distance is adopted as probability measurement, so that the problem that insertion and deletion errors cannot be corrected by a traditional BP decoding algorithm is solved. The inherent problem of an SC framework is also avoided, and the error correction capability is improved; and through parallel operation, the decoding time delay is reduced, and the unit time processing capacity is improved.

Systems and methos for estimating offset of synchronous scramblers are provided. In one aspect, a method of estimating an initial state of a synchronous scrambler in the presence of a linear error control code includes receiving a vector including a transmit bit vector encoded using the linear error control code, and performing nulling on the linear error control code to null impact of the linear error control code from the received vector. The method also includes obtaining a system of equations from the received vector in response to performing the nulling on the linear error control code, and using a min-sum procedure to recover the initial state of the synchronous scrambler from the system of equations.

Systems and methos for estimating offset of synchronous scramblers are provided. In one aspect, a method of estimating an initial state of a synchronous scrambler in the presence of a linear error control code includes receiving a vector including a transmit bit vector encoded using the linear error control code, and performing nulling on the linear error control code to null impact of the linear error control code from the received vector. The method also includes obtaining a system of equations from the received vector in response to performing the nulling on the linear error control code, and using a min-sum procedure to recover the initial state of the synchronous scrambler from the system of equations.

A user equipment (UE) comprises one or more processors and one or more computer-readable storage media coupled to the one or more processors. The one or more computer-readable storage media store instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising: receiving a transport block of data to be transmitted; obtaining modulation and coding scheme (MCS) parameters for the transport block of data; dividing the transport block of data into a plurality of segments; encoding the plurality of segments using inner and outer error control codes based on the MCS parameters; modulating the encoded plurality of segments to produce symbols; and transmitting, via the transmitter, the symbols using one or more resource elements.

The present disclosure relates to a data processor and a method of operating a data processor that is operable to execute programs to perform data processing operations, and in which plural execution threads may be grouped together into thread groups in which an instruction is executed upon one or more execution threads of a thread group.